參數(shù)資料
型號(hào)： EFM32TG108F32
廠商： Energy Micro
文件頁數(shù)： 91/136頁
文件大小： 0K
描述： MCU 32BIT 32KB FLASH 24-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 17
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 24-VQFN 裸露焊盤
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 914-1032-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
58
www.energymicro.com
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the
result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of
the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Section 3.5.1.6 (p. 59) .
Note
ADDW
is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to
the SUB syntax that uses the imm12 operand.
3.5.1.3 Restrictions
In these instructions:
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
Rn must also be SP
any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
you must not specify the S suffix
Rm must not be PC and must not be SP
if the instruction is conditional, it must be the last instruction in the IT block
with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB,
and only with the additional restrictions:
you must not specify the S suffix
the second operand must be a constant in the range 0 to 4095.
Note
When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded
to b00 before performing the calculation, making the base address for the calculation
word-aligned.
If you want to generate the address of an instruction, you have to adjust the constant
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler automatically
calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
bit[0] of the value written to the PC is ignored
a branch occurs to the address created by forcing bit[0] of that value to 0.
3.5.1.4 Condition flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.
3.5.1.5 Examples
ADD
R2, R1, R3
SUBS
R8, R6, #240
; Sets the flags on the result
RSB
R4, R4, #1280
; Subtracts contents of R4 from 1280
ADCHI
R11, R0, R3
; Only executed if C flag set and Z
; flag clear
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EFM32TG108F32-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 24QFN
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