參數(shù)資料
型號: EFM32TG108F32
廠商: Energy Micro
文件頁數(shù): 87/136頁
文件大?。?/td> 0K
描述: MCU 32BIT 32KB FLASH 24-QFN
特色產(chǎn)品: EFM32 Tiny Gecko
標準包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: EBI/EMI,I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 17
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 24-VQFN 裸露焊盤
包裝: 標準包裝
其它名稱: 914-1032-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
54
www.energymicro.com
PUSH
and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access
based on SP, and with the final address for the access written back to the SP. PUSH and POP are the
preferred mnemonics in these cases.
3.4.7.2 Operation
PUSH
stores registers on the stack in order of decreasing the register numbers, with the highest
numbered register using the highest memory address and the lowest numbered register using the lowest
memory address.
POP
loads registers from the stack in order of increasing register numbers, with the lowest numbered
register using the lowest memory address and the highest numbered register using the highest memory
address.
See Section 3.4.6 (p. 52) for more information.
3.4.7.3 Restrictions
In these instructions:
reglist must not contain SP
for the PUSH instruction, reglist must not contain PC
for the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
if the instruction is conditional, it must be the last instruction in the IT block.
3.4.7.4 Condition flags
These instructions do not change the flags.
3.4.7.5 Examples
PUSH
{R0,R4#R7}
PUSH
{R2,LR}
POP
{R0,R10,PC}
3.4.8 LDREX and STREX
Load and Store Register Exclusive.
3.4.8.1 Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
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