參數(shù)資料
型號： EFM32TG108F32
廠商： Energy Micro
文件頁數(shù)： 102/136頁
文件大?。?/td> 0K
描述： MCU 32BIT 32KB FLASH 24-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 17
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 24-VQFN 裸露焊盤
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： 914-1032-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
68
www.energymicro.com
3.6.1.5 Examples
MUL
R10, R2, R5
; Multiply, R10 = R2 x R5
MLA
R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
MULS
R0, R2, R2
; Multiply with flag update, R0 = R2 x R2
MULLT
R2, R3, R2
; Conditionally multiply, R2 = R3 x R2
MLS
R4, R5, R6, R7
; Multiply with subtract, R4 = R7 - (R5 x R6)
3.6.2 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32#bit operands and producing
a 64#bit result.
3.6.2.1 Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
UMULL
Unsigned Long Multiply.
UMLAL
Unsigned Long Multiply, with Accumulate.
SMULL
Signed Long Multiply.
SMLAL
Signed Long Multiply, with Accumulate.
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
RdHi, RdLo
are the destination registers. For UMLAL and SMLAL they also hold
the accumulating value.
Rn, Rm
are registers holding the operands.
3.6.2.2 Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these
integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits
of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these
integers, adds the 64#bit result to the 64#bit unsigned integer contained in RdHi and RdLo, and writes
the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It
multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most
significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It
multiplies these integers, adds the 64#bit result to the 64#bit signed integer contained in RdHi and RdLo,
and writes the result back to RdHi and RdLo.
3.6.2.3 Restrictions
In these instructions:
do not use SP and do not use PC
RdHi and RdLo must be different registers.
3.6.2.4 Condition flags
These instructions do not affect the condition code flags.
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