參數(shù)資料
型號： EFM32TG108F32
廠商： Energy Micro
文件頁數(shù)： 12/136頁
文件大小： 0K
描述： MCU 32BIT 32KB FLASH 24-QFN
特色產(chǎn)品： EFM32 Tiny Gecko
標準包裝： 1
系列： Tiny Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 17
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 24-VQFN 裸露焊盤
包裝： 標準包裝
其它名稱： 914-1032-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
109
www.energymicro.com
Bits
Name
Function
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that tried to perform the illegal load of the PC.
[1]
INVSTATE
Invalid state usage fault:
0 = no invalid state usage fault
1 = the processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
[0]
UNDEFINSTR
Undefined instruction usage fault:
0 = no undefined instruction usage fault
1 = the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined
instruction.
An undefined instruction is an instruction that the processor cannot decode.
Note
The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are
set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
4.3.12 Hard Fault Status Register
The HFSR gives information about events that activate the hard fault handler. See the register summary
in Table 4.12 (p. 94) for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing 1 to
any bit clears that bit to 0. The bit assignments are:
31 30
2 1 0
Reserved
29
DEBUGEVT
FORCED
VECTTBL
Reserved
Table 4.29. HFSR bit assignments
Bits
Name
Function
[31]
DEBUGEVT
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise
behavior is Unpredictable.
[30]
FORCED
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that
cannot be handles, either because of priority or because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find
the cause of the fault.
[29:2]
-
Reserved.
[1]
VECTTBL
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
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