參數(shù)資料
型號(hào): EBD26UC6AKSA-6B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: Single Pole Normally Open: 1-Form-A
中文描述: 32M X 64 DDR DRAM MODULE, 0.7 ns, ZMA200
封裝: LEAD FREE, SODIMM-200
文件頁數(shù): 14/19頁
文件大?。?/td> 213K
代理商: EBD26UC6AKSA-6B-E
EBD26UC6AKSA-E
Preliminary Data Sheet E0605E10 (Ver. 1.0)
14
Timing Parameter Measured in Clock Cycle for unbuffered DIMM
Number of clock cycle
tCK
6ns
7.5ns
Parameter
Symbol
min.
max.
min.
max.
Unit
Write to pre-charge command delay (same bank)
tWPD
4 + BL/2
3 + BL/2
tCK
Read to pre-charge command delay (same bank)
tRPD
BL/2
BL/2
tCK
Write to read command delay (to input all data)
tWRD
2 + BL/2
2 + BL/2
tCK
Burst stop command to write command delay
(CL = 2)
tBSTW
2
tCK
(CL = 2.5)
tBSTW
3
3
tCK
Burst stop command to DQ High-Z
(CL = 2)
tBSTZ
2
2
tCK
(CL = 2.5)
tBSTZ
2.5
2.5
2.5
2.5
tCK
Read command to write command delay
(to output all data)
(CL = 2)
tRWD
2 + BL/2
tCK
(CL = 2.5)
tRWD
3 + BL/2
3 + BL/2
tCK
Pre-charge command to High-Z
(CL = 2)
tHZP
2
2
tCK
(CL = 2.5)
tHZP
2.5
2.5
2.5
2.5
tCK
Write command to data in latency
tWCD
1
1
1
1
tCK
Write recovery
tWR
3
2
tCK
DM to data in latency
tDMD
0
0
0
0
tCK
Mode register set command cycle time
tMRD
2
2
tCK
Self refresh exit to non-read command
tSNR
12
10
tCK
Self refresh exit to read command
tSRD
200
200
tCK
Power down entry
tPDEN
1
1
1
1
tCK
Power down exit to command input
tPDEX
1
1
tCK
相關(guān)PDF資料
PDF描述
EBD26UC6AKSA-7A-E Single Pole Normally Open: 1-Form-A, 400V
EBD26UC6AKSA-6B 256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)
EBD26UC6AKSA Single Pole Normally Open: 1-Form-A
EBD26UC6AKSA-7A Single Pole Normally Open: 1-Form-A, 800V
EBD26UC6AKSA-7B Single Pole Normally Open: 1-Form-A
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