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參數(shù)資料
| 型號： | EBD26UC6AKSA-6B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | Single Pole Normally Open: 1-Form-A |
| 中文描述： | 32M X 64 DDR DRAM MODULE, 0.7 ns, ZMA200 |
| 封裝： | LEAD FREE, SODIMM-200 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 213K |
| 代理商： | EBD26UC6AKSA-6B-E |
EBD26UC6AKSA-E
Preliminary Data Sheet E0605E10 (Ver. 1.0)
12
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Note
Input capacitance
CI1
Address, /RAS, /CAS, /WE
45
pF
Input capacitance
CI2
CK, /CK, CKE, /CS
48
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
18
pF
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Symbol
min.
max.
min.
max.
min.
max
Unit
Notes
Clock cycle time
(CL = 2)
tCK
7.5
12
7.5
12
10
12
ns
10
(CL = 2.5)
tCK
6
12
7.5
12
7.5
12
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min
(tCH, tCL)
—
min
(tCH, tCL)
—
min
(tCH, tCL)
—
tCK
DQ output access time from
CK, /CK
DQS output access time from CK,
/CK
tAC
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
2, 11
tDQSCK –0.6
0.6
–0.75
0.75
–0.75
0.75
ns
2, 11
DQS to DQ skew
tDQSQ
—
0.45
—
0.5
—
0.5
ns
3
DQ/DQS output hold time from
DQS
tQH
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
ns
Data hold skew factor
tQHS
—
0.55
—
0.75
—
0.75
ns
Data-out high-impedance time from
CK, /CK
Data-out low-impedance time from
CK, /CK
tHZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
5, 11
tLZ
–0.7
0.7
–0.75
0.75
–0.75
0.75
ns
6, 11
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQ and DM input setup time
tDS
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input hold time
tDH
0.45
—
0.5
—
0.5
—
ns
8
DQ and DM input pulse width
tDIPW
1.75
—
1.75
—
1.75
—
ns
7
Write preamble setup time
tWPRES 0
—
0
—
0
—
ns
Write preamble
tWPRE
0.25
—
0.25
—
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
9
Write command to first DQS
latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time tDSS
0.2
—
0.2
—
0.2
—
tCK
DQS falling edge hold time from
CK
tDSH
0.2
—
0.2
—
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
0.35
—
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
0.35
—
0.35
—
tCK
Address and control input setup
time
tIS
0.75
—
0.9
—
0.9
—
ns
8
Address and control input hold time tIH
0.75
—
0.9
—
0.9
—
ns
8
Address and control input pulse
width
tIPW
2.2
—
2.2
—
2.2
—
ns
7
相關PDF資料 |
PDF描述 |
|---|---|
| EBD26UC6AKSA-7A-E | Single Pole Normally Open: 1-Form-A, 400V |
| EBD26UC6AKSA-6B | 256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks) |
| EBD26UC6AKSA | Single Pole Normally Open: 1-Form-A |
| EBD26UC6AKSA-7A | Single Pole Normally Open: 1-Form-A, 800V |
| EBD26UC6AKSA-7B | Single Pole Normally Open: 1-Form-A |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EBD26UC6AKSA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks) |
| EBD26UC6AKSA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks) |
| EBD26UC6AKSA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks) |
| EBD26UC6AKSA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks) |
| EBD26UC6AKSA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks) |
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