參數資料
| 型號： | DS3170+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 183/230頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX DS3/E3 100-CSBGA |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 640 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | DS3，E3 |
| 電路數： | 1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 120mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LBGA，CSBGA |
| 供應商設備封裝： | 100-CSBGA（11x11） |
| 包裝： | 托盤 |
| 包括： | DS3 調幀器，E3 調幀器，HDLC 控制器，芯片內 BERT |
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DS3170 DS3/E3 Single-Chip Transceiver
56 of 230
10.2.1.1.1 LIU Enabled, Loop Timing Enabled
In this mode, the receive LIU sources the clock for both the receive and transmit logic. The RCLKO, TCLKO and
TLCLK clock output pins will be the same. The transmit or receive line payload signal pins can be timed to any of
these clock. The use of the RCLKO pin as the timing source is suggested. If RCLKO is used as the timing source,
be sure to set PORT.CR3.RFTS = 0 for output timing.
10.2.1.1.2 LIU Disabled, Loop Timing Enabled
In this mode, the RLCLK pin are the source of the clock for both the receive and transmit logic. The RCLKO,
TCLKO and TLCLK clock output pins will both be the same as the RLCLK clock. The transmit or receive line
payload signals can be timed to any of these clock pins. The use of the RLCLK pin as the timing source is
suggested. If RLCLK is used as the timing source, be sure to set PORT.CR3.RFTS = 1 for input timing.
10.2.1.2 Loop Timing Disabled
When loop timing is disabled, the transmit clock source can be different than the receive clock source. The
loopback functions, LLB, PLB and DLB, will cause the clock sources to switch when they are activated. Care must
be taken when selecting the clock reference for the transmit and receive signals.
The most versatile clocking option has the receive line interface signals timed to RLCLK, the transmit line interface
signals timed to TLCLK, the receive framer signals timed to RCLKO, and the transmit framer signals timed to
TCLKO. This clocking arrangement works in all modes.
When LLB is enabled, the clock on the TLCLK pin will switch to the clock from the RLCLK pin or RX LIU. It is
recommended that the transmit line interface signals be timed to the TLCLK pins. If TLCLK is used as the timing
source, be sure to set PORT.CR3.TLTS = 0 for output timing.
When PLB is enabled, the TCLKI pin will not be used and the internal transmit clock is switched to the internal
receive clock. The clock on the TCLKO pin will switch to the clock from the RLCLK pins or RX LIU. The framer
input signals will be ignored while PLB is enabled. It is recommended that the transmit line interface signals be
timed to the TCLKO pins.
When DLB is enabled, the internal receive clock is switched to the internal transmit clock which is sourced from the
TCLKI pin or one of the CLAD clocks, and the clock on the RLCLK pin or from the RX LIU will not be used. The
clock on the RCLKO pin will switch to the clock on the TCLKI pins or one of the CLAD clocks. The receive line
signals from the RX LIU or line interface pins will be ignored. It is recommended that the receive framer pins be
timed to the RCLKO pin. If TCLKO is used as the timing source, be sure to set PORT.CR3.TFTS = 0 for output
timing.
When both DLB and LLB are enabled, the TLCLK clock pin are connected to either the RX LIU recovered clock or
the RLCLK clock pin, and the RCLKO clock pin will be connected to the TCLKI clock pin or one of the CLAD
clocks. It is recommended that the transmit line signals be timed to the TLCLK pin, the receive line interface signals
be timed to the RLCLK pin, the receive framer signals be timed to the RCLKO pin, and the transmit framer signals
be timed to the TCLKO pin.
10.2.1.2.1 LIU Enabled - CLAD Timing Disabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and the TCLKI pin sources the clock for the
transmit logic.
10.2.1.2.2 LIU Enabled - CLAD Timing Enabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
10.2.1.2.3 LIU Disabled - CLAD Timing Disabled – no LB
In this mode, the RLCLK pin source the clock for the receive logic and the TCLKI pin sources the clock for the
transmit logic.
10.2.1.2.4 LIU Disabled - CLAD Timing Enabled – no LB
In this mode, the RLCLK pin source the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
相關PDF資料 |
PDF描述 |
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| DS3181N+ | IC ATM/PACKET PHY W/LIU 400PBGA |
| DS32512N+ | IC LIU DS3/E3/STS-1 12P 484-BGA |
| DS3254N+ | IC LIU DS3/E3/STS-1 144-CSBGA |
| DS33M33N+ | IC MAPPER ETHERNET 256CSBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS3170_11 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:DS3/E3 Single-Chip Transceiver Single-Chip Transceiver for DS3 and E3 |
| DS3170+ | 功能描述:網絡控制器與處理器 IC DS3/E3 Single-Chip Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3170DK | 功能描述:網絡開發(fā)工具 DS3170 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數據速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS3170L | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:DS3/E3 Single-Chip Transceiver |
| DS3170LN | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:DS3/E3 Single-Chip Transceiver |
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