參數(shù)資料
型號: DS31256+
廠商: Maxim Integrated Products
文件頁數(shù): 169/183頁
文件大?。?/td> 0K
描述: IC CTRLR HDLC 256-CHANNEL 256BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: HDLC 控制器
接口: 串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 500mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(27x27)
包裝: 管件
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DS31256 256-Channel, High-Throughput HDLC Controller
86 of 183
On an HDLC-channel basis in the receive DMA configuration RAM, the host instructs the DMA how to
use the large and small buffers for the incoming packet data on that particular HDLC channel. The host
has three options: (1) only use large buffers, (2) only use small buffers, or (3) first fill a small buffer,
then, if the incoming packet requires more buffer space, use one or more large buffers for the remainder
of the packet. The host selects the option through the size field in the receive configuration RAM
(Section 9.2.5). Large buffers are best used for data-intensive, time-insensitive packets like graphics
files, whereas small buffers are best used for time-sensitive information like real-time voice.
Table 9-B. Receive DMA Main Operational Areas
DESCRIPTORS
FUNCTION
SECTION
Packet
A dedicated area of memory that describes the location and attributes of
the packet data.
Free Queue
A dedicated area of memory that the host writes to inform the DMA
where to store incoming packet data.
Done Queue
A dedicated area of memory that the DMA writes to inform the host
that the packet data is ready for processing.
The done-queue descriptors contain information that the DMA wishes to pass to the host. Through the
done-queue descriptors, the DMA informs the host about the incoming packet data and where to find the
packet descriptors that it has written into main memory. Each completed descriptor contains the starting
address of the data buffer where the packet data is stored.
If enabled, the DMA can burst read the free-queue descriptors and burst write the done-queue
descriptors. This helps minimize PCI bus accesses, freeing the PCI bus up to do more time critical
functions. See Sections 9.2.3 and 9.2.4 for more details about this feature.
Receive DMA Actions
A typical scenario for the receive DMA is as follows:
1) The receive DMA gets a request from the receive FIFO that it has packet data that needs to be sent to
the PCI bus.
2) The receive DMA determines whether the incoming packet data should be stored in a large buffer or
a small buffer.
3) The receive DMA then reads a free-queue descriptor (either by reading a single descriptor or a burst
of descriptors), indicating where, in main memory, there exists some free data buffer space and
where the associated free packet descriptor resides.
4) The receive DMA starts storing packet data in the previously free buffer data space by writing it out
through the PCI bus.
5) When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it
can calculate this), it then reads another free-queue descriptor to find another free data buffer and
packet descriptor location.
6) The receive DMA then writes the previous packet descriptor and creates a linked list by placing the
current descriptor in the next descriptor pointer field; it then starts filling the new buffer location.
Figure 9-1 provides an example of packet descriptors being link listed together (see channel 2).
7) This continues until the entire packet data is stored.
8) The receive DMA either waits until a packet has been completely received or until a programmable
number (from 1 to 7) of data buffers have been filled before writing the done-queue descriptor, which
indicates to the host that packet data is ready for processing.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS31256+ 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256B 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC