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| 型號： | DS31256+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 112/183頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 控制器類型： | HDLC 控制器 |
| 接口： | 串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 500mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
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Bits 7 to 11/BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These bits select which port has the dedicated
resources of the BERT.
00000 = Port 0
01000 = Port 8
10000 = Port 0 (high speed)
11000 = n/a
00001 = Port 1
01001 = Port 9
10001 = Port 1 (high speed)
11001 = n/a
00010 = Port 2
01010 = Port 10
10010 = Port 2 (high speed)
11010 = n/a
00011 = Port 3
01011 = Port 11
10011 = n/a
11011 = n/a
00100 = Port 4
01100 = Port 12
10100 = n/a
11100 = n/a
00101 = Port 5
01101 = Port 13
10101 = n/a
11101 = n/a
00110 = Port 6
01110 = Port 14
10110 = n/a
11110 = n/a
00111 = Port 7
01111 = Port 15
10111 = n/a
11111 = n/a
Bit 12/Receive FIFO Priority Control Bit 0 (RFPC0); Bit 13/Receive FIFO Priority Control Bit 1 (RFPC1).
These bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest priority to the
DMA to transfer data from the FIFO to the PCI bus. In the priority decoded scheme, the lower the HDLC channel
numbers, generally the higher the priority. In schemes ’10 and ’11, the upper priority decode channels have
priority over the lower priority decode channels.
00 = all HDLC channels are serviced round robin
01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin
10 = HDLC channels 16 to 1 are priority decoded; HDLC channels 17-up are round robin
11 = HDLC channels 64 to 1 are priority decoded; HDLC channels 65-up are round robin
Bit 14/Transmit FIFO Priority Control Bit 0 (TFPC0); Bit 15/Transmit FIFO Priority Control Bit 1
(TFPC1). These two bits select the algorithm the FIFO uses to determine which HDLC channel gets the highest
priority to the DMA to transfer data from the PCI bus to the FIFO. In the schemes ’01 and ‘11m upper priority
decode channels have priority over the lower priority decode channels.
00 = all HDLC channels are serviced round robin
01 = HDLC channels 1 to 3 are priority decoded; other HDLC channels are round robin
10 = HDLC channels 16 to 1 are priority decoded; other HDLC channels 17-up re round robin
11 = HDLC channels 64 to 1 are priority decoded; other HDLC channels 65-up are round robin
5.3 Status and Interrupt
5.3.1 General Description of Operation
There are three status registers in the device: status master (SM), status for the receive V.54 loopback
detector (SV54), and status for DMA (SDMA). These registers report events in real-time by setting a bit
within the register to 1. All bits that have been set within the register are cleared when the register is
read, and the bit is not set again until the event has occurred again. Each bit can generate an interrupt at
the PCI bus through the
PINTA output signal pin, and, if the local bus is in the configuration mode, then
an interrupt also be created at the
LINT output signal pin. Each status register has an associated interrupt
mask register, which can allow/deny interrupts from being generated on a bit-by-bit basis. All status
registers remain active even if the associated interrupt is disabled.
SM Register
The status master (SM) register reports events that occur at the port interface, at the BERT receiver, at
the PCI bus, and at the local bus. See Figure 5-1 for details.
The port interface reports change-of-frame alignment (COFA) events. If the software detects that one of
these bits is set, the software must begin polling the RP[n]CR or TP[n]CR registers of each active port (a
maximum of 16 reads) to determine which port or ports has incurred a COFA. Also, the host can
allow/deny the COFA indications to be passed to the SRCOFA and STCOFA status bits through the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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