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| 型號： | DS31256+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 100/183頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 控制器類型： | HDLC 控制器 |
| 接口： | 串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 500mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應商設備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
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these signals are always outputs during the address phase. They remain outputs for the data phase(s) in a write
transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs
during the address phase. They remain inputs for the data phase(s) in a read transaction and become outputs for a
write transaction. When the device is not involved in a bus transaction, these signals remain tri-stated. These
signals are always updated and sampled on the rising edge of PCLK.
Signal Name:
PCBE0/PCBE1/PCBE2/PCBE3
Signal Description:
PCI Bus Command and Byte Enable
Signal Type:
Input/Output (tri-state capable)
Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals
define the bus command. During the data phase, these signals are used as byte enables. During data phases,
PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is high, the associated byte is
invalid; when low, the associated byte is valid. When the device is an initiator, this signal is an output and is
updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the
rising edge of PCLK. When the device is not involved in a bus transaction, these signals are tri-stated.
Signal Name:
PPAR
Signal Description:
PCI Bus Parity
Signal Type:
Input/Output (tri-state capable)
This signal provides information on even parity across both the PAD address/data bus and the PCBE bus
command/byte enable bus. When the device is an initiator, this signal is an output for writes and an input for reads.
It is updated on the rising edge of PCLK. When the device is a target, this signal is an input for writes and an
output for reads. It is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PPAR is tri-stated.
Signal Name:
PFRAME
Signal Description:
PCI Cycle Frame
Signal Type:
Input/Output (tri-state capable)
This active-low signal is created by the bus initiator and is used to indicate the beginning and duration of a bus
transaction.
PFRAME is asserted by the initiator during the first clock cycle of a bus transaction and remains
asserted until the last data phase of a bus transaction. When the device is an initiator, this signal is an output and is
updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the
rising edge of PCLK. When the device is not involved in a bus transaction,
PFRAME is tri-stated.
Signal Name:
PIRDY
Signal Description:
PCI Initiator Ready
Signal Type:
Input/Output (tri-state capable)
The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the
PTRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction,
PIRDY is deasserted when the initiator cannot
temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output
and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on
the rising edge of PCLK. When the device is not involved in a bus transaction,
PIRDY is tri-stated.
Signal Name:
PTRDY
Signal Description:
PCI Target Ready
Signal Type:
Input/Output (tri-state capable)
The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the
PIRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction,
PTRDY is deasserted when the target cannot
temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output
and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled
on the rising edge of PCLK. When the device is not involved in a bus transaction,
PTRDY is tri-stated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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