參數(shù)資料
型號： DS3120N
廠商： Maxim Integrated Products
文件頁數(shù)： 52/133頁
文件大?。?/td> 0K
描述： IC FRAMER T1 28-CHANNEL IND
標準包裝： 1
控制器類型： T1 調幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 300mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 316-BGA
包裝： 管件
DS3112
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2.5 Low-Speed (T1 or E1) Receive Port Signal Description
Signal Name:
LRDAT1 to LRDAT28
Signal Description:
Low-Speed (T1 or E1) Receive Serial Data Outputs
Signal Type:
Output
These output signals present the demultiplexed serial data for the 28 T1 data streams or the 16/21 E1 data
streams. Data can be clocked out of the device either on rising edges (normal clock mode) or falling
edges (inverted clock mode) of the associated LRCLK. This option is controlled via the LRCLKI control
bit in Master Control Register 2 (Section 4.2). Also, the data can be internally inverted before being
output if enabled via the LRDATI control bit in Master Control Register 2 (Section 4.2). When the device
is in the E3 Mode, LRDAT17 to LRDAT28 are meaningless and should be ignored. When the device is
in the G.747 Mode, LRDAT4, LRDAT8, LRDAT12, LRDAT16, LRDAT20, LRDAT24, and LRDAT28
are meaningless and should be ignored. When the M13/E13 multiplexer is disabled, then these outputs are
meaningless and should be ignored.
Signal Name:
LRCLK1 to LRCLK28
Signal Description:
Low-Speed (T1 or E1) Receive Serial Clock Outputs
Signal Type:
Output
These output signals present the demultiplexed serial clocks for the 28 T1 data streams or the 16/21 E1
data streams. The T1 or E1 serial data streams at the associated LRDAT signals can be clocked out of the
device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of LRCLK.
This option is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). When the
device is in the E3 Mode, LRCLK17 to LRCLK28 are meaningless and should be ignored. When the
device is in the G.747 Mode, LRCLK4, LRCLK8, LRCLK12, LRCLK16, LRCLK20, LRCLK24, and
LRCLK28 are meaningless and should be ignored. When the M13/E13 multiplexer is disabled, then these
outputs are meaningless and should be ignored.
Signal Name:
LRDATA/LRDATB
Signal Description:
Low-Speed (T1 or E1) Receive Drop Port Serial Data Outputs
Signal Type:
Output
These two output signals present the demultiplexed serial data from one of the 28 T1 data streams or from
one of the 16/21 E1 data streams (Section 7.4). Data can be clocked out of the device either on rising
edges (normal clock mode) or falling edges (inverted clock mode) of the associated LRCLK. This option
is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data can be
internally inverted before being output if enabled via the LRDATI control bit in Master Control Register
2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless and
should be ignored.
Signal Name:
LRCLKA/LRCLKB
Signal Description:
Low-Speed (T1 or E1) Receive Drop Port Serial Clock Outputs
Signal Type:
Output
These output signals present the demultiplexed serial clocks from one of the 28 T1 data streams or from
one of the 16/21 E1 data streams (Section 7.4). The T1 or E1 serial data streams at the associated LRDAT
signals can be clocked out of the device either on rising edges (normal clock mode) or falling edges
(inverted clock mode) of LRCLK. This option is controlled via the LRCLKI control bit in Master Control
Register 2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless
and should be ignored.
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