參數(shù)資料
型號： DS3120N
廠商： Maxim Integrated Products
文件頁數(shù)： 125/133頁
文件大?。?/td> 0K
描述： IC FRAMER T1 28-CHANNEL IND
標(biāo)準(zhǔn)包裝： 1
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 300mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 316-BGA
包裝： 管件
DS3112
91 of 133
Bit #
Register Name:
THDLC
Register Description:
Transmit HDLC FIFO
Register Address:
84h
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
—
TMEND
Default
—
0
Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always write to the lower byte (bits 0 to 7) first followed
by the upper byte (bits 8 to 15).
Note 2: The THDLC is a write-only register.
Note 3: The Transmit FIFO can be filled to a maximum capacity of 256 bytes. When the Transmit FIFO is full, it will not accept any
additional data.
Bits 0 to 7: Transmit FIFO Data (D0 to D7). Data for the Transmit FIFO can be written to these bits. D0 is the
LSB and is transmitted first while D7 is the MSB and is transmitted last.
Bit 8: Transmit Message End (TMEND). This bit is used to delineate multiple messages in the Transmit FIFO. It
should be set to a one when the last byte of a packet is written to the Transmit FIFO. The setting of this bit
indicates to the HDLC controller that the message is complete and that it should calculate and add in the CRC
checksum and at least two flags. This bit should be set to zero for all other data written to the FIFO. All HDLC
messages must be at least 2 bytes in length.
9.3 HDLC Status and Interrupt Register Description
Register Name:
HSR
Register Description:
HDLC Status Register
Register Address:
86h
Bit #
7
6
5
4
3
2
1
0
Name
TUDR
RPE
RPS
RHWM
—
TLWM
—
TEND
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
RABT
REMPTY
ROVR
TEMPTY
TFL3
TFL2
TFL1
TFL0
Default
—
Note: See Figure 9-1 for details on the signal flow for the status bits in the HSR register. Bits that are underlined are read-only; all other
bits are read-write.
Bit 0: Transmit Packet End (TEND). This latched read-only event-status bit will be set to a one each time the
transmit HDLC controller reads a transmit FIFO byte with the corresponding TMEND bit set or if a FIFO underrun
occurs. This bit will be cleared when read and will not be set again until another message end is detected. The
setting of this bit can cause a hardware interrupt to occur if the TEND bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.
Bit 2: Transmit FIFO Low Watermark (TLWM). This read-only real time status bit will be set to a one when
the transmit FIFO contains less than the number of bytes configured by the Transmit Low Watermark Setting
control bits (TLWMS0 to TLWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO
fills beyond the low watermark. The setting of this bit can cause a hardware interrupt to occur if the TLWM bit in
the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one.
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