參數(shù)資料
型號： DS3112DK
廠商： Maxim Integrated Products
文件頁數(shù)： 113/133頁
文件大小： 0K
描述： KIT DEMO FOR DS3112
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
主要目的： 接口，交叉點開關/多路復用器
已用 IC / 零件： DS3112
已供物品： 板，CD
DS3112
80 of 133
Register Name:
BERTC0
Register Description:
BERT Control Register 0
Register Address:
70h
Bit #
7
6
5
4
3
2
1
0
Name
PBS
TINV
RINV
PS2
PS1
PS0
LC
RESYNC
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
IESYNC
IEBED
IEOF
n/a
RPL3
RPL2
RPL1
RPL0
Default
0
-
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Force Resynchronization (RESYNC). A low to high transition will force the receive BERT synchronizer
to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host
wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent
resynchronization.
Bit 1: Load Bit and Error Counters (LC). A low to high transition latches the current bit and error counts into
the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a
subsequent loads.
Bits 2 to 4: Pattern Select Bits 0 (PS0 to PS2).
If PBS = 0:
000 = Pseudorandom Pattern 2
7 - 1 (ANSI T1.403-1999 Annex B)
001 = Pseudorandom Pattern 2
20 - 1 (non-QRSS)
1 = invert the outgoing data stream
001 = Pseudorandom Pattern 2
11 - 1 (ITU O.153)
010 = Pseudorandom Pattern 2
15 - 1 (ITU O.151)
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = Illegal State
111 = Illegal State
If PBS = 1:
000 = Psuedorandom Pattern 2
9 - 1
010 = Pseudorandom Pattern 2
23 - 1 (ITU O.151)
011 = Illegal State
10X = Illegal State (X = 0 or 1)
11X = lllegal State (X = 0 or 1)
Bit 5: Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6: Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
Bit 7: Pattern Bank Select (PBS)
0 = PS[2:0] select a pattern from Pattern Bank 0
1 = PS[2:0] select a pattern from Pattern Bank 1
相關PDF資料
PDF描述
RMM10DSEN CONN EDGECARD 20POS .156 EYELET
DS2148DK KIT DESIGN LIU DS2148 3/5V T1/E1
H3CWH-6436G IDC CABLE - HKC64H/AE64G/HPL64H
78M6618-PDU-1 EVAL KIT DS8005
RMM10DSEH CONN EDGECARD 20POS .156 EYELET
相關代理商/技術參數(shù)
參數(shù)描述
DS3112N 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*