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參數(shù)資料
| 型號(hào)： | DM164134 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 36/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV PIC18F4XK22 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PIC® 18F |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | PIC18F4XK22，PIC18F2XK22 |
| 所含物品： | 板，文檔 |
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2009 Microchip Technology Inc.
Preliminary
DS41364D-page 287
PIC16F193X/LF193X
REGISTER 23-4:
SSPCON3: SSP CONTROL REGISTER 3
R-0/0
R/W-0/0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ACKTIM:
Acknowledge Time Status bit (I2C mode only)(3)
1
= Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0
= Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6
PCIE
: Stop Condition Interrupt Enable bit (I2C mode only)
1
= Enable interrupt on detection of Stop condition
0
= Stop detection interrupts are disabled(2)
bit 5
SCIE
: Start Condition Interrupt Enable bit (I2C mode only)
1
= Enable interrupt on detection of Start or Restart conditions
0
= Start detection interrupts are disabled(2)
bit 4
BOEN:
Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1
= SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0
= If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode:
This bit is ignored.
In I2C Slave mode:
1
= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0
= SSPBUF is only updated when SSPOV is clear
bit 3
SDAHT:
SDA Hold Time Selection bit (I2C mode only)
1
= Minimum of 300 ns hold time on SDA after the falling edge of SCL
0
= Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2
SBCDE:
Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes idle
1
= Enable slave bus collision interrupts
0
= Slave bus collision interrupts are disabled
bit 1
AHEN:
Address Hold Enable bit (I2C Slave mode only)
1
= Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0
= Address holding is disabled
bit 0
DHEN:
Data Hold Enable bit (I2C Slave mode only)
1
= Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0
= Data holding is disabled
Note 1:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2:
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3:
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
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