參數(shù)資料
型號: DM164134
廠商: Microchip Technology
文件頁數(shù): 107/116頁
文件大?。?/td> 0K
描述: KIT DEV PIC18F4XK22
標準包裝: 1
系列: PIC® 18F
類型: MCU
適用于相關(guān)產(chǎn)品: PIC18F4XK22,PIC18F2XK22
所含物品: 板,文檔
PIC18FXX8
DS41159E-page 88
2006 Microchip Technology Inc.
8.4
IPR Registers
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts. Due to the
number of peripheral interrupt sources, there are three
Peripheral Interrupt Priority registers (IPR1, IPR2 and
IPR3). The operation of the priority bits requires that
the Interrupt Priority Enable bit (IPEN) be set.
REGISTER 8-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
bit 7
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1
=High priority
0
= Low priority
bit 6
ADIP: A/D Converter Interrupt Priority bit
1
=High priority
0
= Low priority
bit 5
RCIP: USART Receive Interrupt Priority bit
1
=High priority
0
= Low priority
bit 4
TXIP: USART Transmit Interrupt Priority bit
1
=High priority
0
= Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1
=High priority
0
= Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1
=High priority
0
= Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
Note 1: This bit is only available on PIC18F4X8 devices. For PIC18F2X8 devices, this bit
is unimplemented and reads as ‘0’.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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