參數(shù)資料
型號(hào)： DC979A
廠商： Linear Technology
文件頁數(shù)： 32/32頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2442
軟件下載： QuikEval System
設(shè)計(jì)資源： DC979A Design File
DC979A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 8k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2442
已供物品： 板
相關(guān)產(chǎn)品： LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP
LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP
LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP
LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP
LTC2442
9
2442fa
For more information www.linear.com/LTC2442
CONVERTER OPERATION
Converter Operation Cycle
The LTC2442 is a multi-channel, high speed,
DS ana-
log-to-digital converter with an easy to use 3- or 4-wire
serial interface (see Figure 1). Its operation is made up
of three states. The converter operating cycle begins with
the conversion, followed by the sleep state and ends with
the data output/input (see Figure 2). The 4-wire interface
consistsofserialdatainput(SDI),serialdataoutput(SDO),
serial clock (SCK) and chip select (CS). The interface,
timing, operation cycle and data out format is compatible
with Linear’s entire family of
DS converters.
Initially, the LTC2442 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
The conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result while operating in the 1X mode. The data output
corresponds to the conversion just performed. This re-
1.69k
SDO
2442 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
1.69k
SDO
2442 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
CONVERT
SLEEP
CHANNEL SELECT
SPEED SELECT
DATA OUTPUT
POWER UP
IN+=CH0, IN–=CH1
OSR=256,1X MODE
2442 F02
CS = LOW
AND
SCK
Figure 2. LTC2442 State Transition Diagram
applications inForMation
test circuits
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