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參數(shù)資料
| 型號： | DC979A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 28/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2442 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC979A Design File DC979A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2442 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP |
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LTC2442
5
2442fa
For more information www.linear.com/LTC2442
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = SEL+ – SEL–, VINCM = (SEL+ + SEL–)/2.
Note 4: FO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in Hz.
Note 11: The converter uses the internal oscillator. FO
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1s (typ) to the
conversion time.
Note 14: In order to achieve optimum linearity, the amplifier power
positive supply input (V+) must exceed the maximum input voltage level by
2V or greater. The negative amplifier power supply input (V–) must be at
least 200mV below the minimum input voltage level.
Note 15: Amplifiers are externally compensated with 0.1F.
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
l
0.1
20
MHz
tHEO
External Oscillator High Period
l
25
10000
ns
tLEO
External Oscillator Low Period
l
25
10000
ns
tCONV
Conversion Time
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
External Oscillator (Notes 10, 13)
l
0.99
126
1.13
145
40 OSR + 170
fEOSC (KHz)
1.33
170
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
l
0.8
0.9
fEOSC/10
1
MHz
Hz
DISCK
Internal SCK Duty Cycle
(Note 9)
l
45
55
%
fESCK
External SCK Frequency Range
(Note 8)
l
20
MHz
fLESCK
External SCK Low Period
(Note 8)
l
25
ns
tHESCK
External SCK High Period
(Note 8)
l
25
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
l
30.9
35.3
320/fEOSC
41.6
s
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 8)
l
32/fESCK
s
t1
CS
↓ to SDO Low Z
(Note 12)
l
0
25
ns
t2
CS
↑ to SDO High Z
(Note 12)
l
0
25
ns
t3
CS
↓ to SCK ↓
(Note 9)
5
s
t4
CS
↓ to SCK ↑
(Note 8, 12)
l
25
ns
tKQMAX
SCK
↓ to SDO Valid
l
25
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
l
15
ns
t5
SCK Setup Before CS
↓
l
50
ns
t6
SCK Hold After CS
↓
l
50
ns
t7
SDI Setup Before SCK
↑
(Note 5)
l
10
ns
t8
SDI Hold After SCK
↑
(Note 5)
l
10
ns
tiMing characteristics
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