If CS remains LOW longer than tEOCtest
參數(shù)資料
型號： DC979A
廠商： Linear Technology
文件頁數(shù)： 13/32頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2442
軟件下載： QuikEval System
設(shè)計(jì)資源： DC979A Design File
DC979A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 8k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2442
已供物品： 板
相關(guān)產(chǎn)品： LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP
LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP
LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP
LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP
LTC2442
20
2442fa
For more information www.linear.com/LTC2442
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
on this first rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 8. On the rising edge of CS, the device
abortsthedataoutputstateandimmediatelyinitiatesanew
conversion. This is useful for systems not requiring all 32
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. Thirteen serial
input data bits are required in order to properly program
the speed/resolution and input channel. If the data output
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next con-
version cycle. If a new channel is being programmed, the
rising edge of CS must come after the 14th falling edge of
SCK in order to store the data input sequence.
Figure 8. Internal Serial Clock, Reduced Data Output Length
CS
SCK
SDI
SDO
BUSY
2442 F08
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 0
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1
0
EN
SGL
0
A0
OSR3 OSR2 OSR1 OSR0 TWOX
ODD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
DON'T CARE
VCC
V+
+INA
MUXOUTA
BUSY
SDO
SDI
EXT
SCK
FO
MUXOUTB
+INB
GND
21
6
7
8
9
28
12
13
11
17
18
10
26
25
4, 5, 32
19
27
2
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
24
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
1F
0.1F
4.5V TO 5.5V
VCC TO 15V
LTC2442
1F
0.1F
CS
–15V TO GND
V–
REF+
REF–
OUTB
–INB
ADCINB
CH0
CH1
CH2
CH3
COM
29
30
31
3
33
1
36
35
OUTA
–INA
ADCINA
4-WIRE
SPI INTERFACE
VCC
applications inForMation
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