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參數(shù)資料
| 型號： | DC979A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2442 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC979A Design File DC979A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2442 |
| 已供物品： | 板 |
| 相關產品： | LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP |
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LTC2442
8
2442fa
For more information www.linear.com/LTC2442
VCC(Pin29):PositiveSupplyVoltage.BypasstoGNDwith
a 10F tantalum capacitor in parallel with a 0.1F ceramic
capacitor as close to the part as possible.
REF+(Pin30),REF–(Pin31):DifferentialReferenceInput.
ThevoltageonthesepinscanhaveanyvaluebetweenGND
and VCC as long as the reference positive input, REF+, is
maintainedmorepositivethanthenegativereferenceinput,
REF–, by at least 0.1V. Bypass to GND with 0.1F Ceramic
capacitor as close to the part as possible.
SDI (Pin 33): Serial Data Input. This pin is used to select
the speed, 1X or 2X mode, resolution and input channel
for the next conversion cycle. At initial power up, the de-
fault mode of operation is CH0-CH1, OSR of 256 and 1X
mode. The serial data input contains an enable bit which
determines if a new channel/speed is selected. If this bit is
low the following conversion remains at the same speed
and selected channel. The serial data input is applied to
the device under control of the serial clock (SCK) during
the data output cycle. The first conversion following a new
channel/speed is valid.
F0 (Pin 34): Frequency Control Pin. Digital input that con-
trols the internal conversion clock. When F0 is connected
to VCC or GND, the converter uses its internal oscillator
running at 9MHz. The conversion rate is determined by
the selected OSR such that tCONV (ms) = 40 OSR + 170/
fOSC (kHz). The first digital filter null is located at 8/tCONV,
7kHz at OSR = 256 and 55Hz (Simultaneous 50Hz/60Hz
at OSR = 32768. This pin may be driven with a maximum
external clock of 10.24MHz resulting in a maximum 8kHz
output rate (OSR = 64, 2X mode).
CS (Pin 35): Active Low Chip Select. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this state as long as CS is
HIGH. A LOW-to-HIGH transition on CS during the Data
Outputabortsthedatatransferandstartsanewconversion.
SDO (Pin 36): Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in
a high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
This signal is HIGH while the conversion is in progress
and goes LOW once the conversion is complete.
AUTOCALIBRATION
AND CONTROL
DIFFERENTIAL
3RD ORDER
Σ MODULATOR
DECIMATING FIR
ADDRESS
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
GND
VCC
CH0
CH1
CH2
CH3
COM
IN+
IN–
SDO
SCK
REF+
ADCINB
ADCINA
OUTB
OUTA
REF–
CS
EXT
SDI
BUSY
FO
2442 F01
–
+
–
+
MUX
–INB
+INB
MUXOUTB
MUXOUTA +INA –INA
AMPB
AMPA
V+
V–
Figure 1. Functional Block Diagram
pin Functions
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