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參數(shù)資料
| 型號： | CXK79M36C160GB-33 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 493K |
| 代理商： | CXK79M36C160GB-33 |
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SONY
ΣRAM
CXK79M72C160GB / CXK79M36C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.1
12 / 28
November 8, 2002
AC Electrical Characteristics
(VDD =1.8V ± 0.1V, VSS =0V, TA =0 to 85
oC)
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise noted.
1. These parameters apply to control inputs E1, E2, E3, ADV, W,and Bx.
2. These parameters are guaranteed by design through extensive corner lot characterization.
3. These parameters are measured at
± 50mV from steady state voltage.
Parameter
Symbol
-33
-4
-5
Units
Notes
MinMax
Input Clock Cycle Time
tKHKH
3.3
---
4.0
---
5.0
---
ns
Input Clock High Pulse Width
tKHKL
1.3
---
1.5
---
2.0
---
ns
Input Clock Low Pulse Width
tKLKH
1.3
---
1.5
---
2.0
---
ns
Address Input Setup Time
tAVKH
0.7
---
0.8
---
1.0
---
ns
Address Input Hold Time
tKHAX
0.4
---
0.5
---
0.5
---
ns
Control Input Setup Time
tBVKH
0.7
---
0.8
---
1.0
---
ns
1
Control Input Hold Time
tKHBX
0.4
---
0.5
---
0.5
---
ns
1
Data Input Setup Time
tDVKH
0.7
---
0.8
---
1.0
---
ns
Data Input Hold Time
tKHDX
0.4
---
0.5
---
0.5
---
ns
Input Clock High to Output Data Valid
tKHQV
---
1.8
---
2.1
---
2.3
ns
Input Clock High to Output Data Hold
tKHQX
0.5
---
0.5
---
0.5
---
ns
2
Input Clock High to Output Data Low-Z
tKHQX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Data High-Z
tKHQZ
---
1.8
---
2.1
---
2.3
ns
2,3
Input Clock High to Output Clock High
tKHCH
0.5
1.8
0.5
2.1
0.5
2.3
ns
Input Clock High to Output Clock Low-Z
tKHCX1
0.5
---
0.5
---
0.5
---
ns
2,3
Input Clock High to Output Clock High-Z
tKHCZ
---
1.8
---
2.1
---
2.3
ns
2,3
Output Clock High to Output Data Valid
tCHQV
---
0.38
---
0.45
---
0.5
ns
2
Output Clock High to Output Data Hold
tCHQX
-0.38
---
-0.45
---
-0.5
---
ns
2
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