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參數(shù)資料
| 型號： | CXK79M36C160GB-33 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 493K |
| 代理商： | CXK79M36C160GB-33 |
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SONY
ΣRAM
CXK79M72C160GB / CXK79M36C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.1
18 / 28
November 8, 2002
Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, con-
troller, etc.), SRAMs, other components, and the printed circuit board.
In conformance with a subset of IEEE std. 1149.1, these devices contain a TAP Controller and four TAP Registers. The TAP
Registers consist of one Instruction Register and three Data Registers (ID, Bypass, and Boundary Scan Registers).
The TAP consists of the following four signals:
TCK:
Test Clock
Induces (clocks) TAP Controller state transitions.
TMS:
Test Mode Select
Inputs commands to the TAP Controller. Sampled on the rising edge of TCK.
TDI:
Test Data In
Inputs data serially to the TAP Registers. Sampled on the rising edge of TCK.
TDO:
Test Data Out
Outputs data serially from the TAP Registers. Driven from the falling edge of TCK.
Disabling the TAP
When JTAG is not used, TCK should be tied “l(fā)ow” to prevent clocking the SRAM. TMS and TDI should either be tied “high”
through a pull-up resistor or left unconnected. TDO should be left unconnected.
Note: Operation of the TAP does not disrupt normal SRAM operation except when the EXTEST-A or SAMPLE-Z instruc-
tion is selected. Consequently, TCK, TMS, and TDI can be controlled any number of ways without adversely affecting the
functionality of the device.
JTAG DC Recommended Operating Conditions
(VDD =1.8V ± 0.1V, TA =0 to 85°C)
JTAG AC Test Conditions
(VDD =1.8V ± 0.1V, TA =0 to 85°C)
Parameter
Symbol
Test Conditions
Min
Max
Units
JTAG Input High Voltage (TCK, TMS, TDI)
VTIH
---
VDD/2 + 0.3
VDD +0.3
V
JTAG Input Low Voltage (TCK, TMS, TDI)
VTIL
---
-0.3
VDD/2 - 0.3
V
JTAG Output High Voltage (TDO)
VTOH
ITOH = -100uA
VDD -0.1
---
V
JTAG Output Low Voltage (TDO)
VTOL
ITOL = 100uA
---
0.1
V
JTAG Output High Voltage (TDO)
VTOH
ITOH =-8mA
VDD -0.4
---
V
JTAG Output Low Voltage (TDO)
VTOL
ITOL =8mA
---
0.4
V
JTAG Input Leakage Current
ITLI
VTIN =VSS to VDD
-20
10
uA
JTAG Output Leakage Current
ITLO
VTOUT =VSS to VDD
-10
10
uA
Parameter
Symbol
Conditions
Units
Notes
JTAG Input High Level
VTIH
1.8
V
JTAG Input Low Level
VTIL
0.0
V
JTAG Input Rise & Fall Time
1.0
V/ns
JTAG Input Reference Level
0.9
V
JTAG Output Reference Level
0.9
V
JTAG Output Load Condition
See Fig. 1 (page 14)
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