- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223633 > CXK79M36C160GB-33 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 PDF資料下載
參數(shù)資料
| 型號： | CXK79M36C160GB-33 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 493K |
| 代理商： | CXK79M36C160GB-33 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁
SONY
ΣRAM
CXK79M72C160GB / CXK79M36C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.1
6 / 28
November 8, 2002
Clock Truth Table
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. “***” indicates that the DQ input requirement or output state and the CQ output state are determined by the previous operation.
3. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
4. If one or more Bx = 0 then B = “T” else B = “F”.
5. DQs are tri-stated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
6. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
7. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four
(4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal ad-
dress wraps back to the initial external (base) address.
CK
E1
(tn)
E
(tn)
ADV
(tn)
W
(tn)
B
(tn)
Previous
Operation
Current Operation
DQ/CQ
(tn)
DQ/CQ
(tn+1)
↑
X
F
0
X
Bank Deselect
***
Hi-Z
↑
X
1
X
Bank Deselect
Bank Deselect (Continue)
Hi-Z
↑
1
T
0
X
Deselect
***
Hi-Z/CQ
↑
X
1
X
Deselect
Deselect (Continue)
Hi-Z/CQ
↑
0T
0
T
X
Write
Loads new address
Stores DQx if Bx =0
***
D1/CQ
↑
0T
0
F
X
Write (Abort)
Loads new address
No data stored
***
X/CQ
↑
X
1
X
T
Write
Write Continue
Increments address by 1
Stores DQx if Bx =0
D1/CQ
D2/CQ
↑
X
1
X
F
Write
Write Continue (Abort)
Increments address by 1
No data stored
D1/CQ
X/CQ
↑
0T
0
1
X
Read
Loads new address
***
Q1/CQ
↑
X
1
X
Read
Read Continue
Increments address by 1
Q1/CQ
Q2/CQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXO-205-66.6666MHZ | CRYSTAL OSCILLATOR, CLOCK, 66.6666 MHz, HCMOS OUTPUT |
| CXO-63GTS2C-FREQ-OUT26 | CRYSTAL OSCILLATOR, CLOCK, 80 MHz - 135 MHz, ACMOS/TTL OUTPUT |
| CXO/IFREQ | CRYSTAL OSCILLATOR, CLOCK, 0.614 MHz - 70 MHz, HCMOS/TTL OUTPUT |
| CXO/IL40.0MHZ | CRYSTAL OSCILLATOR, CLOCK, 40 MHz, HCMOS/TTL OUTPUT |
| CXO/ILTFREQ | CRYSTAL OSCILLATOR, CLOCK, 0.614 MHz - 70 MHz, HCMOS/TTL OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK79M36C161GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (512K x 36) (27 pages 364K Rev. 7/6/01) |
| CXK79M36C162GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-33 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-4 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-5 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。