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參數(shù)資料
| 型號： | CXK79M36C160GB-33 |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 1.8 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 493K |
| 代理商： | CXK79M36C160GB-33 |
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SONY
ΣRAM
CXK79M72C160GB / CXK79M36C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.1
21 / 28
November 8, 2002
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial
output data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: “Instruction Registers” (IR),
which are manipulated via the “IR” states in the TAP Controller, and “Data Registers” (DR), which are manipulated via the
“DR” states in the TAP Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by these devices. It is loaded with the IDCODE in-
struction at power-up, and when the TAP Controller is in the “Test-Logic Reset” and “Capture-IR” states. It is inserted be-
tween TDI and TDO when the TAP Controller is in the “Shift-IR” state, at which time it can be loaded with a new instruction.
However, newly loaded instructions are not executed until the TAP Controller has reached the “Update-IR” state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Bit 0 is the LSB of the Instruction Register, and Bit 2 is the MSB. When the Instruction Register is selected, TDI serially
shifts data into the MSB, and the LSB serially shifts data out through TDO.
Code
(2:0)
Instruction
Description
000
EXTEST-A
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the
B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state.
Also enables the SRAM’s data and clock output drivers, and moves the contents of the B-Scan
Register associated with the data and clock output signals to the input side of the SRAM’s out-
put register. The SRAM’s input clock can then be used to transfer the B-Scan Register contents
directly to the data and clock output pins (the input clock controls the SRAM’s output regis-
ter). Note that newly captured and/or shifted B-Scan Register contents do not appear at the
input side of the SRAM’s output register until the TAP Controller has reached the “Update-
DR” state.
See the Boundary Scan Register description for more information.
001
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register
when the TAP Controller is in the “Capture-DR” state, and inserts the ID Register between
TDI and TDO when the TAP Controller is in the “Shift-DR” state.
See the ID Register description for more information.
010
SAMPLE-Z
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the
B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state.
Also disables the SRAM’s data and clock output drivers.
See the Boundary Scan Register description for more information.
011
PRIVATE
Do not use. Reserved for manufacturer use only.
100
SAMPLE
Loads the individual logic states of all signals composing the SRAM’s I/O ring into the
Boundary Scan Register when the TAP Controller is in the “Capture-DR” state, and inserts the
B-Scan Register between TDI and TDO when the TAP Controller is in the “Shift-DR” state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Do not use. Reserved for manufacturer use only.
110
PRIVATE
Do not use. Reserved for manufacturer use only.
111
BYPASS
Loads a logic “0” into the Bypass Register when the TAP Controller is in the “Capture-DR”
state, and inserts the Bypass Register between TDI and TDO when the TAP Controller is in the
“Shift-DR” state.
See the Bypass Register description for more information.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK79M36C161GB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEMORY-SigmaRAM 16Meg 1x1 LVCMOS I/O (512K x 36) (27 pages 364K Rev. 7/6/01) |
| CXK79M36C162GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-33 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-4 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
| CXK79M36C162GB-5 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36) |
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