參數資料
| 型號： | CS5376A-IQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數： | 30/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER DGTL MULTI-CH 64-TQFP |
| 標準包裝： | 160 |
| 濾波器類型： | 數字 |
| 濾波器數： | 4 |
| 濾波器階數： | 2nd |
| 電源電壓： | 3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（10x10） |
| 包裝： | 管件 |
| 配用： | 598-1778-ND - EVALUATION BOARD FOR CS5376 |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
36
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Interface Control Register
– INTF_CTRL (07h-09h Read, 07h Write, 08h Set, 09h Clear)
These registers control various interface and PHY
features of the FUSB2805. All bits in this register are
viewed as optional features in the ULPI Specification
Rev
1.1;
however,
many
are
supported
by
the
FUSB2805 and are provided for legacy link cores.
Table 18. Interface Control Register
Field Name
Bits Access
Reset
Description
6-pin FsLsSerialMode
6PIN_FSLS_SER
0
rd/wr/s/c
0b
Changes the ULPI interface to 6-pin serial mode. The FUSB2805
must automatically clear this bit when serial mode is exited. It is an
optional mode for support by the ULPI PHY.
A PHY with only four data pins, D[3:0] cannot support this mode.
0b: FS/LS packets are sent using the parallel interface.
1b: FS/LS packets are sent using the 6-pin serial interface
assignments. CLKIN must remain running.
3-pin FsLsSerialMode
3PIN_FSLS_SER
1
rd/wr/s/c
0b
Changes the ULPI interface to 3-pin serial mode. The FUSB2805
must automatically clear this bit when serial mode is exited. It is an
optional mode for support by the ULPI PHY.
0b: FS/LS packets are sent using the parallel interface.
1b: FS/LS packets are sent using the 3-pin serial interface
assignments. CLKIN must remain running.
CarkitMode
(not supported in
FUSB2805)
2
rd/wr/s/c
0b
Reserved
ClockSuspendM
3
rd/wr/s/c
0b
Active LOW clock suspend. Used to output CLOCK in serial
modes. Internal clock circuitry is not powered down and CLKIN
must remain running for serial modes.
0b: Clock is not output in serial modes.
1b: Clock is output in serial modes.
Autoresume
4
rd/wr/s/c
0b
Enables the PHY to automatically transmit resume signaling.
0b: The system is able to wake up its PHY clock in < 1 ms and
Autoresume feature is disabled.
1b: The system is unable to wake up its PHY clock in 1 ms and
Autoresume feature is enabled.
Refer to USB2.0 specification, section 7.1.7.7 and section 7.12 for
more information.
Indicator Complement
IND_COMPL
5
rd/wr/s/c
0b
Tells the FUSB2805 to invert the ExternalVBUSIndicator input
signal, generating the complement output (ie.FAULT).
0b: FUSB2805 does not invert ExternalVBUSIndicator signal
(default).
1b: FUSB2805 inverts ExternalVBUSIndicator signal.
Refer to 3.8.7.3 and Figure 45 of the ULPI Rev. 1.1, October 2004
specification for details.
Indicator Pass Thru
IND_PASS_THRU
6
rd/wr/s/c
0b
Controls whether the complement output is qualified with the
internal VBUSValid comparator before being used in the VBUS state
in the RXCMD.
0b: Complement output signal is qualified with the internal
VBUSValid comparator.
1b: Complement output signal is not qualified with the internal
VBUSValid comparator.
Refer to 3.8.7.3 and Figure 45 of the ULPI Rev. 1.1, October 2004
specification for details.
Continued on the following page
…
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