參數(shù)資料
型號： CS5376A-IQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 29/49頁
文件大小： 0K
描述： IC FILTER DGTL MULTI-CH 64-TQFP
標(biāo)準(zhǔn)包裝： 160
濾波器類型： 數(shù)字
濾波器數(shù)： 4
濾波器階數(shù)： 2nd
電源電壓： 3 V ~ 5 V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 管件
配用： 598-1778-ND - EVALUATION BOARD FOR CS5376
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
35
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
ULPI Registers Specific to FUSB2805
Table 16. Vendor ID and Product ID Registers
Register
Bits
Access Address
Value
Description
VENDOR_ID_LOW
7:0
rd
00h
79h
Lower byte of vendor ID supplied by USB-IF. Fixed
value of 79h.
VENDOR_ID_HIGH
7:0
rd
01h
07h
Upper byte of vendor ID supplied by USB-IF. Fixed
value of 07h.
PRODUCT_ID_LOW
7:0
rd
02h
00h
Lower byte of product ID number. Fixed value of 00h.
PRODUCT_ID_HIGH
7:0
rd
03h
25h
Upper byte of product ID number. Fixed value of 25h.
Function Control Register
– FUNC_CTRL (04h-06h Read, 04h Write, 05h Set, 06h Clear)
These registers control the UTMI function settings of the FUSB2805.
Table 17. Function Control Register
Field Name
Bits
Access
Reset
Description
XcvrSelect
1:0
rd/wr/s/c
01b
Selects the transceiver speed:
00b: Enable HS transceiver
01b: Enable FS transceiver
10b: Enable LS transceiver
11b: Enable FS transceiver for LS packets (FS preamble pre-pended by
default)
TermSelect
2
rd/wr/s/c
0b
Controls the internal 1.5
kΩ pull-up resistor and 45 Ω HS terminations.
Control over the bus resistor changes, as described in Table 4, by the
XcvrSelect, OpMode, DpPulldown, and DmPulldown register settings.
Since LS peripherals never support FS or HS for HS-capable
transceivers, the FUSB2805 does not support providing 1.5 k
on D-.
OpMode
4:3
rd/wr/s/c
00b
Selects the required bit encoding style during transmit.
00b: Normal operation
01b: Non-driving
10b: Disable bit stuffing and NRZI encoding
11b: Do not automatically add SYNC and EOP when transmitting.
Must only be used for HS packets.
Reset
5
rd/wr/s/c
0b
Active HIGH transceiver reset. After the link sets this bit, the FUSB2805
must assert DIR and reset the UTMI+ core. When the reset is
completed, the FUSB2805 de-asserts DIR and automatically clears this
bit. After de-asserting DIR, the FUSB2805 must re-assert DIR and send
an RXCMD update to the link. The link must wait for DIR to de-assert
before using the ULPI bus. Does not reset the ULPI interface or ULPI
register set.
0b: No Reset
1b: Reset
SuspendM
6
rd/wr/s/c
1b
Active LOW PHY suspend. Puts the FUSB2805 into low-power mode.
The FUSB2805 can power down all blocks except the FS receiver, OTG
comparators, and the ULPI interface pins. The FUSB2805 must
automatically set this bit to 1b when low-power mode is exited (prior to
exit STP is asserted by the link).
0b: Low-power mode
1b: Powered
RESERVED
7
rd/wr/s/c
0b
Reserved
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