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參數(shù)資料
| 型號： | CH7012A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7012 TV Output Device |
| 中文描述： | 昆泰CH7012電視輸出設備 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大小： | 551K |
| 代理商： | CH7012A |
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CHRONTEL
Table 1: Pin Description
CH7012A
4
201-0000-042 Rev. 1.1, 9/29/2000
64-Pin
LQFP
36
# Pins
Type
Symbol
Description
1
Out
CVBS
Composite Video
This pin outputs a composite video signal capable of driving a
75 ohm doubly terminated load.
Luma / Green Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be s-video luminance or green
.
Chroma / Red Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be s-video chrominance or red.
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be composite video or blue.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XO. However, an external
clock can drive the XI/FIN input.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XI / FIN. However, if an
external CMOS clock is attached to XI/FIN, XO should be left
open.
Pixel Clock Output
When the CH7012 is operating as a VGA to TV encoder in
master clock mode, this pin provides a pixel clock signal to the
VGA controller which is used as a reference frequency. The
output is selectable between 1X or 2X of the pixel clock
frequency. The output driver is driven from the DVDDV
supply. This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
Buffered Clock Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal
sync. The output is driven from the DVDD supply.
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port
of a graphics controller. The levels are 0 to DVDDV, and the
VREF signal is used as the threshold level.
37
1
Out
Y/G
38
1
Out
C/R
39
1
Out
CVBS/B
42
1
In
XI / FIN
43
1
In
XO
46
1
Out
P-OUT
47
1
Out
BCO
48
1
Out
C/H SYNC
50 – 55,
58 – 63
12
In
D[11] - D[0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CH7012A-T | Chrontel CH7012 TV Output Device |
| CH7202 | MPEG to TV Encoder with 8-bit Input |
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
| CH7301A | Chrontel CH7301 DVI Output Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7012A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7012 TV Output Device |
| CH7013A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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