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參數(shù)資料
| 型號： | CH7012A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7012 TV Output Device |
| 中文描述： | 昆泰CH7012電視輸出設(shè)備 |
| 文件頁數(shù)： | 33/42頁 |
| 文件大?。?/td> | 551K |
| 代理商： | CH7012A |
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201-0000-042 Rev. 1.1, 9/29/2000
33
CHRONTEL
Calculated Increment Value Register
CH7012A
CIV
Symbol:
Address:
11h –
13h
Bits:
8 each
Registers CIV contain the value that was calculated by the CH7012 as the sub-carrier increment value. The entire
bit field, CIV[25:0], is comprised of these three registers plus the MSB values contained in the CIV Control register,
bits CIV25 and CIV24. This value is used when the CIVEN bit is set to ‘1’. The bit locations are specified below.
Register Contents
10hCIV[25:24]
11hCIV[23:16]
12hCIV[15:8]
13hCIV[7:0]
Clock Mode Register
Symbol:
CM
Address:
1Ch
Bits:
4
Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency
(duel edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge
clocking mode).
Bit 1 of register CM controls the P-OUT clock frequency. A value of ‘0’ generates a clock output at the pixel
frequency, while a value of ‘1’ generates a clock at twice the pixel frequency.
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7012. A value of ‘1’ inverts the XCLK
signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
Bit 3 of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S* =
‘1’), the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to
determine the TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to
the TV PLL. The M and N TV PLL divider values are forced to one.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
0
0
0
0
0
0
0
0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
M/S*
R/W
MCP
R/W
PCM
R/W
XCM
R/W
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CH7012A-T | Chrontel CH7012 TV Output Device |
| CH7202 | MPEG to TV Encoder with 8-bit Input |
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
| CH7301A | Chrontel CH7301 DVI Output Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7012A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7012 TV Output Device |
| CH7013A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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