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參數資料
| 型號： | CH7012A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7012 TV Output Device |
| 中文描述： | 昆泰CH7012電視輸出設備 |
| 文件頁數： | 35/42頁 |
| 文件大?。?/td> | 551K |
| 代理商： | CH7012A |
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201-0000-042 Rev. 1.1, 9/29/2000
35
CHRONTEL
CH7012A
Bit 4 of register IDF controls the vertical sync polarity. A value of ‘0’ defines the vertical sync to be active low, and
a value of ‘1’ defines the vertical sync to be active high.
Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7012, and a value
of ‘1’ defines sync to be output from the CH7012. The CH7012 can only output sync signals when operating as a
VGA to TV encoder.
Bit 6 of register IDF signifies when the CH7012 is to decode embedded sync signals present in the input data stream
instead of using the H and V pins. This feature is only available for input data format four. A value of ‘0’ selects the
H and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.
Connection Detect Register
Symbol:
CD
Address:
20h
Bits:
6
The Connection Detect Register provides a means to sense the connection of a TV to the four DAC outputs. The
status bits, DACT[3:0] correspond to the termination of the four DAC outputs. However, the values contained in
these STATUS BITS ARE NOT VALID until a sensing procedure is performed. Use of this register requires a
sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection
sequence works as follows:
1) Set the power management register to enable all DAC’s.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 4
analog outputs are at steady state and no TV synchronization pulses are asserted.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and
the reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be
set if they are CONNECTED.
4) Read the status bits. The status bits, DACT[3:0] now contain valid information which can be read to determine
which outputs are connected to a TV. Again, a “1” indicates a valid connection, a “0” indicates an unconnected
output.
Bit 6 of register CD contains the MSB value for the crystal oscillator adjustment. This control is described in detail
in the DC register description (register 21h).
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved
TYPE:
DEFAULT:
XOSC2 Reserved
R/W
0
DACT3
DACT2
DACT1
DACT0
SENSE
R/W
R/W
R
0
R
0
R
0
R
0
R
0
0
0
相關PDF資料 |
PDF描述 |
|---|---|
| CH7012A-T | Chrontel CH7012 TV Output Device |
| CH7202 | MPEG to TV Encoder with 8-bit Input |
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
| CH7301A | Chrontel CH7301 DVI Output Device |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CH7012A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7012 TV Output Device |
| CH7013A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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