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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁(yè)數(shù)： | 75/222頁(yè) |
| 文件大小： | 974K |
| 代理商： | CD2481 |
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Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
75
7.0
Protocol Processing
The protocols supported by the device depend on the microcode image downloaded at boot time.
This section describes all protocols included in the standard microcode image from Intel.
7.1
HDLC Processing
7.1.1
FCS (Frame Check Sequence)
The FCS is a 16 bit standard computation as used in HDLC, and defined in ISO 3309. This FCS
algorithm is the same used with the synchronous HDLC operation of the CD2481. The basic
characteristics of the FCS are as shown below:
Accumulation:
FCS computation starts after the opening flag and continues to the closing flag.
Polynomial:
The standard polynomial is:
x**16 + x**12 + x**5 + 1
Pre-load:
The FCS 16-bit accumulator is preset to all
‘
1
’
s.
Transmit order:
The FCS bits are identified as X15 to X0. The most-significant bit is X15, and is
transmitted first. Thus, the first FCS character transmitted has bits X15
–
X8 in character positions
D1
–
D8, respectively. The second FCS character has bits X7
–
X0 in character positions D1
–
D8,
respectively.
Transmit polarity:
Inverted.
Correct remainder:
The receiver calculates the entire received frame, including the received FCS
field. If the frame is received error-free, then the correct remainder in the FCS accumulation is
‘
F 0
B 8
’
(X15 is the leftmost bit).
The FCS can be individually enabled or disabled for the transmitter and receiver.
If enabled for the transmitter, the device appends the FCS on transmitted frames. If disabled, the
device adds no FCS at the end of the frame.
If enabled for the receiver, the device computes the received FCS and reports the results. If the FCS
buffer is enabled, the device includes the 2-byte FCS in the received data presented to the host. If
disabled, the device does not test for received FCS.
7.1.2
HDLC Transmit Mode
The transmitter can be programmed to idle in either flag (01111110) or mark (continuous 1's) mode
via Idle bit in Channel Option Register 3 (COR3). When idle in mark is selected, frame
transmission can be programmed to be prepended by a programmable number of pad characters
and a programmable number of flags. The pad character can be selected as either 00 or AA; the pad
characters allow the remote receivers Phase Locked Loop to synchronize quickly to the data. When
NRZI encoding is used, the 00 character guarantees a transition every bit time; for Manchester
encoding, AA guarantees exactly one transition per bit time.
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