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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁(yè)數(shù)： | 53/222頁(yè) |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
53
automatically switches to the other buffer and advances the Receive Current Buffer Address
enough to complete the desired gap. The CD2481 readjusts data alignment in its internal FIFO as
needed to maintain alignment with the external buffer.
Receiver A and B Buffers
In the following drawing, buffers A and B are contained in RAM external to the CD2481. All
others (DMABSTS, ARBADR, ARBCNT, ARBSTS, RCBADR, BRBADR, BRBCNT, and
BRBSTS) are inside the CD2481.
Example 1
Receive a frame from channel 1, no chaining.
1. The host must first make a receive buffer available before a frame can be received. Thus, the
host checks the Nrbuf bit in the DMABSTS register for channel 1 to determine which buffer is
next. In this example, Nrbuf is set to
‘
0
’
indicates buffer A is used next.
2. The host sets up the starting address
—
ARBADR, and the buffer byte count
—
ARBCNT.
When the host writes the count
—
ARBCNT, the host has defined the size limit for the buffer.
3. The host then gives the buffer to the CD2481 by setting the 2481OWN bit in the status register
—
ARBSTS. This notifies the CD2481 that it is now OK to write received.
4. The Rbusy bit in the DMABSTS register for channel 1 is
‘
0
’
until a frame starts to be received.
When frame data starts coming in, the CD2481 sets Rbusy to notify the host that buffer B is
next. As data bytes are written into the buffer, the current buffer pointer, RCBADR, is updated
by the CD2481.
5. At the end of the received frame, the CD2481 tests for correct end of frame delimiter and
CRC. When the received frame is complete, the CD2481 clears the Rbusy bit. In this example,
there is no receive chaining, so the received frame byte count is less than or equal to the buffer
size count
—
ARBCNT. The CD2481 writes the value of the actual received byte count into
Figure 8. Receiver A and B Buffers
CD2481 Transmit
DMA Registers
Physical
Memory
Receiver
Buffer
A
Receiver
Buffer
B
ARBADR (32)
ARBCNT (16)
ARBSTS (8)
(Status Register)
RCBADR (32)
(Currently using Buffer A)
BRBADR (32)
BRBCNT (16)
BRBSTS (8)
(Status Register)
Starting Address
Buffer Byte Count
Current Address
Starting Address
Buffer Byte Count
NOTE:
Number of bits in each register is shown in parentheses (). Buffer A and buffer B do not
need to be the same length.
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