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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁(yè)數(shù)： | 171/222頁(yè) |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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Programmable Four-Channel Communications Controller
—
CD2481
Datasheet
171
Bit 5
rxabt
–
Receive abort
The rxabt bit indicates that an abort sequence (7D
–
7E) has been received.
Bit 4
Reserved; returns
‘
0
’
when read.
Bit 3
OE
–
Overrun error
The OE bit indicates that the receiver buffer and FIFO have been overrun. At least
one new character has been received, but lost since there was no room available in
the receiver buffer and/or FIFO.
Bit 2
FE
–
Framing error
The FE bit indicates that a character has been received with an incorrect Stop bit. The
Stop bit was
‘
0
’
; it should have been
‘
1
’
.
Bit 1
Reserved; returns
‘
0
’
when read.
Bit 0
Break
–
Break detection
The Break bit indicates that a break has been received. A break is a continuous
sequence of at least ten
‘
0
’
bits.
NOTES:
1. During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can only load one of the two timers
in the interrupt service routine.
2. 0E, FE, and break are cumulative over the entire packet in PPP mode. This means that the
respective error occurred somewhere in the packet, but did not cause an immediate interrupt.
9.5.2.4
Receive Interrupt Status Register high (RISRh)
This register is used in DMA mode only.
Bit 7
Bus error (written by CD2481)
0 = No bus error
1 = Bus error was detected on the last transfer
The actual address at which the error occurred is available in the Receive Current
Buffer Address register. In response to a bus error status, the host has two possible
options:
1.Retry from the next position in the buffer.
2.Terminate this buffer by setting TermBuff bit in REOIR, and move onto the next.
Bit 6
Reception of a data frame is complete (Sync DMA mode only).
Register Name: RISRh
Register Description: Receive Interrupt Status Register - High
Default Value: x
’
00
Access: Byte Read Only
Intel Hex Address: x
’
8B
Motorola Hex Address: x
’
88
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Berr
EOF
EOB
0
BA/BB
0
0
0
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