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參數(shù)資料
| 型號(hào)： | CD2481 |
| 廠商： | Intel Corp. |
| 英文描述： | Programmable Four-Channel Communications Controller |
| 中文描述： | 可編程四通道通信控制器 |
| 文件頁(yè)數(shù)： | 18/222頁(yè) |
| 文件大?。?/td> | 974K |
| 代理商： | CD2481 |
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CD2481
—
Programmable Four-Channel Communications Controller
18
Datasheet
BERR*
I
BUS ERROR*:
If this input becomes active while the CD2481 is a bus master, the current bus
cycle will be terminated, the bus relinquished, and an interrupt generated to indicate the error to
the host processor.
A[0
–
7]
I/O (TS)
ADDRESS [0
–
7]:
When the CD2481 is not a bus master, these pins are inputs used to
determine which registers are being accessed, or which interrupt is being acknowledged. When
ADLD* is low, A[0
–
7] output address bits 8
–
15 for external latching. When the CD2481 is a bus
master, A[0
–
7] output the least-significant byte of the transfer address.
A/D[0
–
15]
I/O (TS)
ADDRESS/DATA [0
–
15]:
When the CD2481 is not a bus master, these pins provide the 16-bit
data bus for reading and writing to the CD2481 registers. When ADLD* is low, A/D[0
–
15]
provide the upper address bits for external latching. When the CD2481 is a bus master, A/D[0
–
15] provide a multiplexed address/data bus for reading and writing to system memory.
ADLD*
O (TS)
ADDRESS LOAD*:
This is a strobe used to externally latch the upper portion of the system
address bus A[8
–
31]. While ADLD* is low, address bits 16
–
31 are available on A/D[0
–
15], and
address bits 8
–
15 on A[0
–
7].
AEN*
O (TS)
ADDRESS ENABLE*:
This output is used to output enable the external address bus drivers
during CD2481 DMA cycles.
DATEN*
O (TS)
DATA ENABLE*:
This output is active when either the CD2481 is a bus master, or the CS* and
DS* pins are low. It is used to enable the external data bus buffers during host register read/
write operations or during DMA operations. For operations on 32-bit buses, this signal needs to
be gated with A[1] to select the correct half of the data bus.
DATDIR*
O (TS)
DATA DIRECTION*:
This output is active when either the CD2481 is a bus master, or the CS*
pin is low. It is used to control the external data buffers; when low, the buffers should be enabled
in the CD2481 to system bus direction.
CLK
I
CLOCK:
System clock.
BUSCLK
O
BUS CLOCK:
This is the system clock divided by two, which is used internally to control certain
bus operations. This pin is driven low during hardware reset.
RESET*
I
RESET*:
This signal should stay valid for a minimum of 20 ns. The reset state of the CD2481
will be guaranteed at the rising edge of this signal. When RESET* is removed, the CD2481 also
performs a software initialization of its registers.
TEST
I
TEST:
In normal operation, this pin should be kept low. For board-level testing purposes, it
provides a mechanism for forcing normal output pins to High-Impedance mode. When the TEST
pin is high, the following pins will be in High-Impedance mode: BUSCLK, BGOUT*, IACKOUT*,
RXCOUT[0
–
3], RTS*[0
–
3], DTR*[0
–
3], and TXD[0
–
3].
To ensure that all CD2481 outputs are high-impedance, either of the following two conditions
must be met: the RESET* pin can be driven low, and the TEST pin driven high; or the CD2481
is kept in the bus idle state (not accessed for read/write operations nor DMA active), and the
TEST pin is driven high.
RTS*[0
–
3]
O
REQUEST TO SEND* [0
–
3]:
This output can be controlled automatically by the CD2481 to
indicate that data is ready to be sent on the TXD pin.
TXCOUT/DTR*
O
TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0
–
3]:
This output can be controlled
automatically by the CD2481 to indicate that a programmable threshold has been reached in the
receive FIFO. It can also be programmed to output the transmit data clock. Following reset, this
pin will be high and stays high in Clock mode until the transmit channel is enabled for the first
time; after that it remains active independent of the state of the transmit enable. In all modes,
the clock transitions every bit time, even during idle fill in Asynchronous mode. Data transitions
are made on the negative going edge of TXCOUT.
RXCOUT[0
–
3]
O
RECEIVE CLOCK OUT [0
–
3]:
This output provides a one-time bit rate clock for the receive data
in all modes, except when an input (RXCIN) one-time receive clock is used. After reset, this pin
will be low until the channel is receive enabled for the first time, after which it remains active,
independent of the state of receive-enable. When in Asynchronous mode, the output only
transitions while receiving data and not during inter-character fill. The receive data is sampled
on the positive-going edge of this clock.
Table 1. Pin Descriptions
(Sheet 2 of 3)
Symbol
Type
Description
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