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參數(shù)資料
| 型號： | BU-65527M4-200 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 2094K |
| 代理商： | BU-65527M4-200 |
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Data Device Corporation
www.ddc-web.com
BU-65528 and BU-65527
F1 web-10/02-0
TABLE 30. RT MODE BLOCK STATUS WORD
11
BIT
DESCRIPTION
15(MSB) EOM
14
SOM
13
CHANNEL B/A
12
ERROR FLAG
10
FORMAT ERROR
9
NO RESPONSE TIMEOUT
8
LOOP TEST FAIL
7
DATA STACK ROLLOVER
6
ILLEGAL COMMAND WORD
5
WORD COUNT ERROR
4
INCORRECT SYNC
3
INVALID WORD
RT-RT FORMAT
2
RT-RT GAP/SYNC/ADDRESS ERROR
1
RT-RT 2ND COMMAND ERROR
0(LSB)
COMMAND WORD CONTENTS ERROR
Note: TABLES 29 to 32 are not registers. They are WORDS stored in
RAM.
TABLE 31. WORD MONITOR IDENTIFICATION WORD
8
BIT
DESCRIPTION
15(MSB) GAP TIME
7
WORD FLAG
6
THIS RT
5
BROADCAST
4
ERROR
3
COMMAND/DATA
2
CHANNEL B/A
1
CONTIGUOUS DATA/GAP
0(LSB)
MODE CODE
GAP TIME
TABLE 32. MESSAGE MONITOR MODE BLOCK STATUS WORD
11
BIT
DESCRIPTION
15(MSB) EOM
14
SOM
13
CHANNEL B/A
12
ERROR FLAG
10
FORMAT ERROR
9
NO RESPONSE TIMEOUT
8
GOOD DATA BLOCK TRANSFER
7
DATA STACK ROLLOVER
6
RESERVED
5
WORD COUNT ERROR
4
INCORRECT SYNC
3
INVALID WORD
RT-RT TRANSFER
2
RT-RT GAP/SYNC/ADDRESS ERROR
1
RT-RT 2ND COMMAND ERROR
0(LSB)
COMMAND WORD CONTENTS ERROR
BC CONTROLLER (BC) ARCHITECTURE
The BC protocol of the BU-65528/27 implements all MIL-STD-
1553B message formats. Message format is programmable on a
message-by-message basis by means of bits in the BC Control
Word and the
bit of the Command Word for the respective
message. The BC Control Word allows 1553 message format,
1553A/B type RT, bus channel, self-test, and Status Word mask-
ing to be specified on an individual message basis. In addition,
automatic retries and/or interrupt requests may be enabled or
disabled for individual messages. The BC performs all error
checking required by MIL-STD-1553B. This includes validation of
response time, sync type and sync encoding, Manchester II
encoding, parity, bit count, word count, Status Word RT Address
field, and various RT-to-RT transfer errors. The BU-65528/27's
BC response timeout value is programmable with choices of 18,
22, 50, and 130
s. The longer response timeout values allow for
operation over long buses and/or the use of repeaters.
FIGURE 2 illustrates BC message gap and frame timing. The
BU-65528/27 may be programmed to process BC frames of up
to 512 messages with no processor intervention. It is possible to
program for either single frame or frame auto-repeat operation.
In the auto-repeat mode, the frame repetition rate may be con-
trolled either internally, using a programmable BC frame timer, or
from an external trigger input. The internal BC frame time is pro-
grammable up to 6.55 seconds in increments of 100
s. In addi-
tion to BC frame time, message gap time, defined as the start of
the current message to the start of the subsequent message, is
programmable on an individual message basis. The time
between individual successive messages is programmable up to
65.5
s, in increments of 1 s.
BC MEMORY ORGANIZATION
TABLE 33 illustrates a typical memory map for BC mode. It is
important to note that the only fixed locations for the BU-
65528/27 in the Standard BC mode are for the two Stack
Pointers (address locations 0100 and 0104 hex) and for the two
Message Count locations (0101 and 0105 hex). Enabling the
Frame Auto-Repeat mode will reserve four more memory loca-
tions for use in the Enhanced BC mode; these locations are for
the two Initial Stack Pointers (address locations 102 and 106
hex) and for the Initial Message Count locations (103 and 107
hex). The user is free to locate the Stack and BC Message
Blocks anywhere else within the 64K (4K internal) shared RAM
address space.
For simplicity of illustration, assume the allocation of the maxi-
mum length of a BC message for each message block in the typ-
ical BC memory map of TABLE 33. The maximum size of a BC
message block is 38 words, for an RT-to-RT transfer of 32 Data
Words (Control + 2 Commands + Loopback + 2 Status Words +
32 Data Words). Note, however, that this example assumes the
disabling of the 256-word boundaries.
BC MEMORY MANAGEMENT
FIGURE 3 illustrates the BU-65528/27's BC memory manage-
ment scheme. One of the BC memory management features is
the global-double-buffering mechanism. This provides for two
sets of the various BC mode data structures: Stack Pointer and
Message Counter locations, Descriptor Stack areas, and BC
R
/
T
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