參數(shù)資料
型號(hào)： BU-65527M4-200
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA
文件頁數(shù)： 28/32頁
文件大?。?/td> 2094K
代理商： BU-65527M4-200
5
Data Device Corporation
www.ddc-web.com
BU-65528 and BU-65527
F1 web-10/02-0
mode). The base address of the shared RAM within the selected
address space (A24 or A32) is software programmable through
the use of the offset register.
Each 1553 channel contains its own set of independent regis-
ters. The registers for each channel on a card are contiguous.
TABLE 3 illustrates the register address map for a card consist-
ing of four 1553 channels. The register definitions are the same
for each channel. Through the use of the offset register, the
shared memory for each channel may be programmed to have a
unique base address in the A24 or A32 address space.
Definition of the address mapping and accessibility for the BU-
65528/27's 22 non-test registers, and the test registers, is as fol-
lows:
ID/Logical Address Register, and Device Type Register:
Defined by VXI specification. These Read-Only registers are
used to provide device information to the host processor.
Status/Control Register: Defined by VXI specification. Used to
reset the card and to enable the card's memory.
Offset Register: Defined by VXI specification. Used to program
the base address of the card's 12K x 16 of shared RAM in either
the A24 or A32 address space.
Vector/Level Register: Used to program the interrupt priority
level and to define the 8-bit interrupt vector that the card will sup-
ply during an interrupt acknowledge cycle.
Interrupt Mask Register: Used to enable and disable interrupt
requests for various conditions.
Configuration Registers #1 and #2: Used to select the BU-
65528/27's mode of operation, and for software control of RT
Status Word bits, Active Memory Area, BC Stop-on-Error, RT
Memory Management mode selection, and control of the Time
Tag operation.
Start/Reset Register: Used for “command” type functions, such
as software reset, BC/MT Start, Interrupt Reset, Time Tag Reset,
and Time Tag Register Test. The Start/Reset Register includes
provisions for stopping the BC in its auto-repeat mode, either at
the end of the current message or at the end of the current BC
frame.
BC/RT Command Stack Pointer Register: Allows the host
CPU to determine the pointer location for the current or most
recent message when the BU-65528/27 is in BC or RT modes.
BC Control Word/RT Subaddress Control Word Register: In
BC mode, allows host access to the current or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and speci-
fy MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current, or most recent,
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the ACE.
TABLE 3. A16 ADDRESS MAPPING
HEX ADDRESS
DESCRIPTION/ACCESSIBILITY
0000,0001
ID/Logical Address Register (RD) for Channel #1
0002,0003
Device Type Register (RD) for Channel #1
0004,0005
Status/Control Register (RD/WR) for Channel #1
0006,0007
Offset Register (RD/WR) for Channel #1
0008,0009
Vector/Level (RD/WR) for Channel #1
000A,000B
Reserved
000C,000D
Reserved
000E,000F
Reserved
0010,0011
Interrupt Mask Register (RD/WR) for Channel #1
0012,0013
Configuration Register #1 (RD/WR) for Channel #1
0014,0015
Configuration Register #2 (RD/WR) for Channel #1
0016,0017
Start/Reset Register (WR) for Channel #1
0016,0017
Command Stack Pointer Register (RD) for Ch. #1
0018.0019
BC Ctrl Wd/RT Subaddr Ctrl Wd (RD/WR) for Ch. #1
001A,001B
Time Tag Register (RD/WR) for Channel #1
001C,001D
Interrupt Status Register (RD) for Channel #1
001E,001F
Configuration Register #3 (RD/WR) for Channel #1
0020,0021
Configuration Register #4 (RD/WR) for Channel #1
0022,0023
Configuration Register #5 (RD/WR) for Channel #1
0024,0025
RT/MT Data Stack Addr Reg. (RD/WR) for Ch. #1
0026,0027
BC Frame Time Remaining Register (RD) for Ch. #1
0028,0029
BC Time Remaining to Next Msg Reg. (RD) Ch. #1
002A,002B
BC Frame Time/RT Last Command/MT Trigger Word
Register (RD/WR) for Channel #1
002C,002D
RT Status Word Register (RD) for Channel #1
002E,002F
RT BIT Word Register (RD) for Channel #1
0030,0031
Test Mode Register #0 for Channel #1
0032,0033
Test Mode Register #1 for Channel #1
0034,0035
Test Mode Register #2 for Channel #1
0036,0037
Test Mode Register #3 for Channel #1
0038,0039
Test Mode Register #4 for Channel #1
003A,003B
Test Mode Register #5 for Channel #1
003C,003D
Test Mode Register #6 for Channel #1
003E,003F
Test Mode Register #7 for Channel #1
0040,0041
ID/Logical Address Register for Channel #2
007E,007F
Test Mode Register #7 for Channel #2
0080,0081
ID/Logical Address Register for Channel #3
00BE,00BF
Test Mode Register #7 for Channel #3
00C0,00C1
ID/Logical Address Register for Channel #4
00FE,00FF
Test Mode Register #7 for Channel #4
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