參數(shù)資料
型號(hào)： BU-64743G8-200
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝： 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80
文件頁數(shù)： 58/93頁
文件大?。?/td> 585K
代理商： BU-64743G8-200
61
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
A11
B9
Lower 12 bits of 16-bit bi-directional address bus.
In both the buffered and transparent modes, the host CPU accesses
Mark3 registers and internal RAM by means of A11 - A0 (4K ver-
sions). For 64K versions, A15-A12 are also used for this purpose.
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transpar-
ent mode, A12-A0 (or A15-A0) are inputs during CPU accesses and
become outputs, driving outward (towards the CPU) when the 1553
protocol/memory management logic accesses up to 64K words of
external RAM.
In transparent mode, the address bus is driven outward only when the
signal DTACK is low (indicating that the Mark3 has control of the RAM
interface bus) and IOEN is high, indicating a non-host access. Most of
the time, including immediately after power turn-on, A12-A0 (or A15-
A0) will be in high impedance (input) state.
E6
A10
A8
C15
A09
B7
C10
A08
C9
D10
A07
C7
D9
A06
D7
V9
A05
C6
C12
A04
D8
B7
A03
D6
E9
A02
E8
C9
A01
E7
U8
A00
F10
F8
TABLE 61. PROCESSOR ADDRESS BUS (CONT.)
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
BU-64743B8
BU-64843B8
BU-64863B8
BALL
4K RAM
(BU-64743B8
BU-6484XBX)
64K RAM
(BU-6486XBX)
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相關(guān)PDF資料
PDF描述
BU-65142D1-240L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-260Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-340Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-370Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-370 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
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