參數(shù)資料
型號(hào)： BU-64743G8-200
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝： 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80
文件頁(yè)數(shù)： 30/93頁(yè)
文件大?。?/td> 585K
代理商： BU-64743G8-200
36
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
15
13
0
BLOCK STATUS WORD
TIME TAG WORD
DATA BLOCK POINTER
RECEIVED COMMAND
WORD
CONFIGURATION
REGISTER #1
MONITOR COMMAND
STACK POINTERS
MONITOR
COMMAND STACKS
CURRENT
AREA B/A
MONITOR DATA
STACKS
MONITOR DATA
BLOCK #N + 1
MONITOR DATA
BLOCK #N
CURRENT
COMMAND WORD
MONITOR DATA
STACK POINTERS
IF THIS BIT IS "0" (NOT SELECTED)
NO WORDS ARE STORED IN EITHER
THE COMMAND STACK OR DATA STACK.
IN ADDITION, THE COMMAND AND DATA
STACK POINTERS WILL NOT BE UPDATED.
NOTE
SELECTIVE MONITOR
LOOKUP TABLES
SELECTIVE MONITOR
ENABLE
(SEE NOTE)
OFFSET BASED ON
RTA4-RTA0, T/R, SA4
FIGURE 11. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
MISCELLANEOUS
CLOCK INPUT
The Mini-ACE Mark3 decoder is capable of operating from a 10,
12, 16, or 20 MHz clock input. Depending on the configuration
of the specific model Mini-ACE Mark3 terminal, the selection of
the clock input frequency may be chosen by one of either two
methods. For all versions, the clock frequency may be specified
by means of the host processor writing to Configuration
Register #6. With the second method, which is applicable only
for the versions incorporating 4K (but not 64K) words of internal
RAM, the clock frequency may be specified by means of the
input signals that are otherwise used as the A15 and A14
address lines.
ENCODER/DECODERS
For the selected clock frequency, there is internal logic to derive
the necessary clocks for the Manchester encoder and decoders.
For all clock frequencies, the decoders sample the receiver out-
puts on both edges of the input clock. By in effect doubling the
decoders' sampling frequency, this serves to widen the tolerance
to zero-crossing distortion, and reduce the bit error rate.
For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773
applications), the decoders are capable of operating with single-
ended, rather than double-ended, input signals. The standard
transceiverless version (BU-64XXXX0) of the Mini-ACE Mark3 is
internally strapped for single-ended input signals. For applica-
tions involving the use of double-ended transceivers, it is sug-
gested that you contact the factory at DDC regarding a double-
ended transceiverless version of the Mini-ACE Mark3.
TIME TAG
The Mini-ACE Mark3 includes an internal read/writable Time Tag
Register. This register is a CPU read/writable 16-bit counter with
a programmable resolution of either 2, 4, 8, 16, 32, or 64 s per
LSB. Another option allows software controlled incrementing of
the Time Tag Register. This supports self-test for the Time Tag
相關(guān)PDF資料
PDF描述
BU-65142D1-240L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-260Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-340Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-370Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D1-370 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
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