參數(shù)資料
型號(hào)： BU-64743G8-200
廠商： DATA DEVICE CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80
封裝： 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80
文件頁(yè)數(shù)： 47/93頁(yè)
文件大?。?/td> 585K
代理商： BU-64743G8-200
51
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
A11
1
Lower 12 bits of 16-bit bi-directional address bus.
In both the buffered and transparent modes, the host CPU accesses Mark3 registers and internal RAM by
means of A11 - A0 (4K versions). For 64K versions, A15-A12 are also used for this purpose.
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-A0 (or A15-A0) are
inputs during CPU accesses and become outputs, driving outward (towards the CPU) when the 1553 pro-
tocol/memory management logic accesses up to 64K words of external RAM.
In transparent mode, the address bus is driven outward only when the signal DTACK is low (indicating that
the Mark3 has control of the RAM interface bus) and IOEN is high, indicating a non-host access. Most of
the time, including immediately after power turn-on, A12-A0 (or A15-A0) will be in high impedance (input)
state.
A10
2
A09
75
A08
7
A07
12
A06
27
A05
74
A04
78
A03
13
A02
19
A01
33
A00 (LSB)
18
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
A13 /
+3.3V/+5.0V
LOGIC
77
For 64K RAM versions, this signal is always configured as address line A13. Refer to
the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as A13.
For 4K RAM versions, if UPADDREN is connected to logic "0", then this signal MUST
be connected to +3.3V-LOGIC (logic "1") for the BU-64XX3 or +5.0V (logic "1") for the
BU-64XX5.
A13
A12 / RTBOOT
76
For 64K RAM versions, this signal is always configured as address line A12. Refer to
the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as
A12.
For 4K RAM versions, if UPADDREN is connected to logic "0", then this signal func-
tions as RTBOOT. If RTBOOT is connected to logic "0", the Mark3 will initialize in RT
mode with the Busy status word bit set following power turn-on. If RTBOOT is hard-
wired to logic "1", the Mark3 will initialize in either Idle mode (for an RT-only part), or in
BC mode (for a BC/RT/MT part).
A12
TABLE 52. PROCESSOR ADDRESS BUS (CONT.)
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
4K RAM
(BU-6474XF/GX
BU-6484XF/GX)
64K RAM
(BU-64863F/GX)
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
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