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參數(shù)資料
| 型號： | BU-64743G8-200 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | 22.35 X 22.35 MM, 3.30 MM HEIGHT, CERAMIC, QFP-80 |
| 文件頁數(shù)： | 46/93頁 |
| 文件大小： | 585K |
| 代理商： | BU-64743G8-200 |
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50
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
A15 /
CLK_SEL_1
A15 (MSB)
73
16-bit bi-directional address bus.
For 64K RAM versions, this signal is always configured as address line A15 (MSB).
Refer to the description for A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as
address line A15.
For 4K RAM versions, if UPADDREN is connected to logic "0", this signal operates as
CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Mark3 clock frequency, as follows:
CLK_SEL_1
CLK_SEL_0
Clock Frequency
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
A14 /
CLK_SEL_0
A14
80
For 64K RAM versions, this signal is always configured as address line A14. Refer to
the description of A11-A0 below.
For 4K RAM versions, if UPADDREN is connected to logic "1", this signal operates as
A14.
For 4K RAM versions, if UPADDREN is connected to logic "0", then this signal oper-
ates as CLK_SEL_0. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Mark3 clock frequency, as defined in the description for A15/CLK_SEL1 above.
TABLE 52. PROCESSOR ADDRESS BUS
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
4K RAM
(BU-6474XF/GX
BU-6484XF/GX)
64K RAM
(BU-64863F/GX)
16-bit bi-directional data bus.This bus interfaces the host processor to the Mini-ACE Mark3's internal regis-
ters and internal RAM. In addition, in transparent mode, this bus allows data transfers to take place
between the internal protocol/memory management logic and up to 64K x 16 of external RAM. Most of the
time, the outputs for D15 through D0 are in the high impedance state. They drive outward in the buffered or
transparent mode when the host CPU reads the internal RAM or registers.
Also, in the transparent mode, D15-D0 will drive outward (towards the host) when the protocol/management
logic is accessing (either reading or writing) internal RAM, or writing to external RAM. In the transparent
mode, D15-D0 drives inward when the CPU writes internal registers or RAM, or when the protocol/memory
management logic reads external RAM.
D10
60
D9
57
D8
52
D7
53
D6
41
D5
49
D4
43
D3
48
D2
47
D1
42
D0 (LSB)
46
D15 (MSB)
59
D14
56
D13
54
D12
55
D11
58
TABLE 51. DATA BUS
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
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