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參數(shù)資料
| 型號(hào)： | BU-62843 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？ |
| 文件頁數(shù)： | 8/56頁 |
| 文件大?。?/td> | 368K |
| 代理商： | BU-62843 |
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8
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
FIFO NOT EMPTY
When set to '1', indicates that the write FIFO is not empty.
BAR1 DRR_DATA_DISCARD
If the data discard timer times out while waiting for a retry on a
BAR1 access, this bit will be set. If BAR1 read is discarded, it
may have caused an action (for example clearing an ACE inter-
rupt) that has not been recognized by the PCI MASTER.
FAIL-SAFE ERROR
If not in FAIL_SAFE OFF mode and fail-safe error occurs (ACE
does not respond), this bit will be set. Fail-safe errors are
extremely unlikely.
DRR_HOLD
When '0', a delayed read request is discarded if the PCI
Enhanced Mini-ACE has obtained requested data and a different
transaction is requested. When '1', delayed read request is held
until master repeats original request or timeout occurs.
BITS 30 - 22
Reserved, write as 0s.
PCI ENHANCED MINI-ACE INTERRUPT ENABLE
Must be set to "1".
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE
Enables interrupt to occur on a BAR1 delayed read timeout.
FAIL-SAFE INTERRUPT ENABLE
When set to a "1", an interrupt is generated if not in FAILSAFE
OFF mode and a fail-safe error is detected.
FAIL-SAFE INTERRUPT AUTOCLEAR ENABLE
If set, causes interrupt and the FAIL_SAFE ERROR bit (REG0-
bit 22) to be cleared whenever upper word of REG0 is read by
the PCI MASTER. If not set, bit 1 in Reg 7 must be used to clear
fail-safe interrupts.
000-0FC
100-7FC
800
804
808
80C
810
814
818
81C
820-FFC
ACE
—
REG0
REG1
REG2
REG3
REG4
REG5
REG6
REG7
—
TABLE 8. (BAR1) ACE / CONTROL REGISTERS - 4K
BYTE TOTAL SPACE
ADDRESS
OFFSET
PCI ENHANCED MINI-ACE Register Space
RESERVED (Target-Abort if accessed)
GLOBAL ACTIVITY (RD)
FAIL-SAFE OPERATION / INTERRUPT (RD/WR)
FAIL-SAFE TIMER (RD)
FAIL-SAFE TIMER PRELOAD (RD/WR)
DISCARD TIMER (RD)
DISCARD TIMER PRELOAD (RD/WR)
GENERAL PURPOSE, CUSTOMER USE (RD/WR)
CLEAR FAIL-SAFE INT/RESET ACE (WR)
RESERVED (Target-Abort if accessed)
NAME
DEFINITION / ACCESSIBILITY
31 (MSB)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
0 (LSB)
PCI INTERRUPT ACTIVE
FIFO NOT EMPTY
0
0
0
0
0
1
BAR1 DRR_DATA_DISCARD
FAIL_SAFE ERROR
0
0
0
0
0
PCI ENHANCED MINI-ACE INTERRUPT ACTIVE
0
0
TABLE 9. REG0 GLOBAL ACTIVITY REGISTER
(READ 800H)
BIT
DESCRIPTION
This register will be all 0s after RST#, except for bit 24.
31 (MSB)
30
22
21
20
19
18
17
16
15
0 (LSB)
DRR_HOLD
RESERVED, WRITE AS 0
RESERVED, WRITE AS 0
PCI ENHANCED MINI-ACE INTERRUPT ENABLE
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE
FAILSAFE INTERRUPT ENABLE
FAILSAFE INTERRUPT AUTOCLEAR ENABLE
FAILSAFE MODE - BIT 1 (MSB)
FAILSAFE MODE - BIT 0 (LSB)
RESERVED, WRITE AS 0
RESERVED, WRITE AS 0
TABLE 10. REG1 FAIL-SAFE OPERATION /
INTERRUPT REGISTER (READ/WRITE 804H)
BIT
DESCRIPTION
This register will be all 0s after RST#, except that bit 17 will be 1 (Failsafe mode =
Failsafe Halt). Note that Fail-safe errors are extremely unlikely.
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