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參數(shù)資料
| 型號： | BU-62843 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強迷你ACE論壇？ |
| 文件頁數(shù)： | 42/56頁 |
| 文件大?。?/td> | 368K |
| 代理商： | BU-62843 |
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42
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
1
2
3
4
5
6
7
th
tsu
tv
tv
th
tsu
th
tsu
th
th
tsu
tsu
tsu
th
tsu
ADDRS
PCI single read from PACE configuration space (C/BE# = Ah)
with PCI timing parameters. AD[31:0]: address driven by master; data driven by PACE
DATA
ByteEnables
Ah
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
I
IDSEL
FIGURE 13. PCI SINGLE READ OF CONFIGURATION SPACE WITH TIMING
FIGURE 13 illustrates a PCI read from the PACE's configuration space. The PACE only responds to Type Zero configuration access:
AD[1:0] must be 00 during the command phase.The PACE will drive a full Dword on the AD lines independent of which byte enables
are asserted during the configuration read.
tv
CLK to signal valid delay
tsu
Input setup time to CLK
th
Input hold time from CLK
TABLE 62. PCI INTERFACE TIMINGS
SYMBOL
PARAMETER
2
7
0
MIN
11
MAX
ns
ns
ns
UNITS
FIGURE 14 illustrates a PCI single write to PACE configuration space. The PACE only responds to Type Zero configuration access:
AD[1:0] must be 00 during the command phase. Note that all combinations of byte enables for configuration writes are supported. If
no byte enables are asserted during a burst write to configuration space no internal write will occur, but the internal address will be
incremented.
1
2
3
4
5
6
PCI single write to PACE configuration space (C/BE# = Bh)
ADRS
DATA
Bh
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD[31:0]
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
I
IDSEL
FIGURE 14. PCI SINGLE WRITE TO CONFIGURATION SPACE
TABLE 62 provides the timing parameters for 3.3V PCI signaling
environments applicable to the PACE, and FIGURE 13 shows
the timing reference points. The timing parameters apply to the
other timing diagrams, but are not illustrated. The PACE con-
forms to revision 2.2 of the PCI Local Bus specification.The tim-
ing parameters are provided here for ease of reference only.
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| BU-62864 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
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