參數(shù)資料
型號： BU-62843
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強迷你ACE論壇？
文件頁數(shù)： 4/56頁
文件大?。?/td> 368K
代理商： BU-62843
4
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1.PCI ENHANCED MINI-ACE SPECIFICATIONS
(CONT.)
MHz
MHz
MHz
MHz
MHz
%
%
%
%
33.3
0.01
0.10
0.001
0.01
-0.01
-0.10
-0.001
-0.01
CLOCK INPUTS
PCI Clock Input Frequency
1553 Clock Frequency
Default Mode
Option
Option
Option
Long Term Tolerance
1553A Compliance
1553B Compliance
Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next Message
(for Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
16.0
12.0
10.0
20.0
TABLE 1 NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance and
Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins
TX/RX_A(B) and TX/RX_A(B) of the PCI Enhanced Mini-ACE hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are connected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input.The applicable frequency range is 75 kHz to 1 MHz.
in.
(mm)
oz
(g)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
0.6
(17)
°C/W
°C
°C
°C
μs
μs
μs
μs
μs
μs
μs
μs
μs
150
150
+300
19.5
23.5
51.5
131
7
8.4
2.5
9.5
10.0
to
10.5
18.5
22.5
50.5
129.5
660.5
-55
-65
17.5
21.5
49.5
127
4
PHYSICAL CHARACTERISTICS
72-Pin, Ceramic Flatpack / Gull Lead
Size
Weight
THERMAL
72-Pin, Ceramic Flatpack / Gull Lead
Thermal Resistance, Junction-to-Case,
Hottest Die (
θ
JC
) (Note 12)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
BC/RT/MT Response Timeout (Note 10)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
TABLE 1 NOTES: (Cont’d)
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub side
(either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8)
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 μs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses dur-
ing BC Start-of-Message (SOM) and End-of-Message (EOM) trans-
fer sequences could have the effect of lengthening the intermessage
gap time. For each host access during an SOM or EOM sequence,
the intermessage gap time will be lengthened by 6 clock cycles.
Since there are 7 internal transfers during SOM and 5 during EOM,
this could theoretically lengthen the intermessage gap by up to 72
clock cycles; i.e., up to 7.2 μs with a 10 MHz clock, 6.0 μs with a 12
MHz clock, 4.5 μs with a 16 MHz clock, or 3.6 μs with a 20 MHz clock.
(9)
For Enhanced BC mode, the typical value for intermessage gap time
is approximately 10 clock cycles longer than for the non-enhanced
BC mode. That is, an addition of 1.0 μs at 10 MHz, 833 ns at 12
MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12)
θ
jcis measured to the bottom of the case.
(13) External 10 μF tantalum and 0.1 μF capacitors should be located as
close as possible to Pins 20 and 72, and a 0.1 μF at pin 37.The BU-
62864 should also have a 0.1 μF at pin 26.
(14) MIL-STD-1760 requires that the PCI Enhanced Mini-ACE produce a
20 Vp-p minimum output on the stub connection.
(15) Power dissipation specifications assume a transformer coupled con-
figuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
(16) The 5V tolerant pins are CLOCK_IN, RTAD0-5, RTAD_PAR,
RTAD_LAT, TXINH_A/B, and SSFLAG/EXT_TRIG.
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