參數(shù)資料
型號(hào): ATAM893T-TKSYD
廠(chǎng)商: Atmel
文件頁(yè)數(shù): 43/98頁(yè)
文件大小: 0K
描述: IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線(xiàn),3 線(xiàn))
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類(lèi)型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
48
4680C–4BMCU–01/05
ATAM893-D
A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter
starts counting triggered by the external signal at its input. In single-action mode, the counter
counts only one time up to the programmed compare match event. These modes are very useful
for modulation, demodulation, signal generation, signal measurement and phase control. For
phase control, the timer input is protected against negative voltages and has zero-cross detec-
tion capability.
Timer 3 has a modulator output stage and input functions for demodulation. As modulator it
works together with Timer 2 or the serial interface. When the shift register is used for modulation
the data shifted out of the register is encoded bit-wise. In all demodulation modes, the decoded
data bits are shifted automatically into the shift register.
Figure 5-25. Counter 3 Stage
5.3.3.2
Timer/Counter Modes
Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via the Timer
3 Mode Register T3M.
In all these modes, the compare register and the compare-mode register belonging to it define
the counter value for a compare match and the action of a compare match. A match of the cur-
rent counter value with the content of one compare register triggers a counter reset, a Timer 3
interrupt or the toggling of the output flip-flop. The compare mode registers T3M1 and T3M2
contain the mask bits for enabling or disabling these actions.
The counter can also be enabled to execute single actions with one or both compare registers. If
this mode is set the corresponding compare match event is generated only once after the
counter starts.
8-bit comparator
Compare register 1
RES
Capture register
8-bit counter
Compare register 2
Control
C31
C32
Control
T3SM1
NQ
D
T3RM1
T3IM1
T3TM1
TOG2
T3I
T3TM2
T3IM2
T3RM2
T3SM2
NQ
D
CL3
T3EIM
TOG3
INT5
CM31
CM32
: T3M1
: T3M2
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