參數(shù)資料
型號: AT90S4433-8AC
廠商: Atmel
文件頁數(shù): 95/126頁
文件大?。?/td> 0K
描述: IC MCU 4K FLSH 8MHZ A/D 32TQFP
標準包裝: 250
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
包裝: 托盤
70
AT90S/LS4433
1042H–AVR–04/03
Scanning Multiple
Channels
Since change of analog channel always is delayed until a conversion is finished, the
Free Run mode can be used to scan multiple channels without interrupting the con-
verter. Typically, the ADC Conversion Complete interrupt will be used to perform the
channel shift. However, the user should take the following fact into consideration: The
interrupt triggers once the result is ready to be read. In Free Run mode, the next conver-
sion will start immediately when the interrupt triggers. If ADMUX is changed after the
interrupt triggers, the next conversion has already started and the old setting is used.
ADC Noise Canceling
Techniques
Digital circuitry inside and outside the AT90S4433 generates EMI, which might affect
the accuracy of analog measurements. If conversion accuracy is critical, the noise level
can be reduced by applying the following techniques:
1.
The analog part of the AT90S4433 and all analog components in the application
should have a separate analog ground plane on the PCB. This ground plane is
connected to the digital ground plane via a single point on the PCB.
2.
Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane and keep them well away from high-speed switching
digital tracks.
3.
The AVCC pin on the AT90S4433 should be connected to the digital V
CC supply
voltage via an LC network as shown in Figure 49.
4.
Use the ADC Noise Canceler function to reduce induced noise from the CPU.
5.
If some Port C pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
Figure 49. ADC Power Connections
Note that since AVCC feeds the Port C output drivers, the RC network shown should not
be employed if any Port C serve as outputs.
28
27
26
25
24
23
22
21
20
19
PC5 (ADC5)
PC4 (ADC4)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
AGND
AREF
AVCC
PB5
VCC
100 nF
Analog
Ground
Plane
AT90S4433
10
H
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