參數(shù)資料
型號: AT90S4433-8AC
廠商: Atmel
文件頁數(shù): 59/126頁
文件大?。?/td> 0K
描述: IC MCU 4K FLSH 8MHZ A/D 32TQFP
標(biāo)準(zhǔn)包裝: 250
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
包裝: 托盤
38
AT90S/LS4433
1042H–AVR–04/03
Timer/Counter1 Control
Register B – TCCR1B
Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the Input Capture trigger Noise Canceler function
is disabled. The Input Capture is triggered at the first rising/falling edge sampled on the
ICP (Input Capture Pin) as specified. When the ICNC1 bit is set (one), four successive
samples are measured on the ICP (Input Capture Pin), and all samples must be
high/low according to the input capture trigger specification in the ICES1 bit. The actual
sampling frequency is the XTAL clock frequency.
Bit 6 – ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the Input Capture Pin (ICP). While
the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Cap-
ture Register (ICR1) on the rising edge of the Input Capture Pin (ICP).
Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a Compare Match. If the CTC1 control bit is cleared, Timer/Counter1 contin-
ues counting and is unaffected by a Compare Match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used
and the Compare Register is set to C, the timer will count as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 1, 1| ...
In PWM mode, this bit has no effect.
Bit
7
6
5
4
3
2
1
0
$2E ($4E)
ICNC1
ICES1
CTC1
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value
0
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