參數(shù)資料
型號(hào): AT90S4433-8AC
廠商: Atmel
文件頁數(shù): 70/126頁
文件大小: 0K
描述: IC MCU 4K FLSH 8MHZ A/D 32TQFP
標(biāo)準(zhǔn)包裝: 250
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 4KB(2K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
包裝: 托盤
48
AT90S/LS4433
1042H–AVR–04/03
Serial Peripheral
Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the AT90S4433 and peripheral devices or between several AVR devices. The
AT90S4433 SPI features include the following:
Full Duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Four Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Figure 36. SPI Block Diagram
The interconnection between Master and Slave CPUs with SPI is shown in Figure 37.
The PB5(SCK) pin is the clock output in the Master mode and is the clock input in the
Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock
generator, and the data written shifts out of the PB3(MOSI) pin and into the PB3(MOSI)
pin of the Slave CPU. After shifting one byte, the SPI clock generator stops, setting the
end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Slave Select input, PB2(SS), is set low to
select an individual Slave SPI device. The two Shift Registers in the Master and the
Slave can be considered as one distributed 16-bit circular Shift Register. This is shown
in Figure 37. When data is shifted from the Master to the Slave, data is also shifted in
the opposite direction, simultaneously. This means that during one shift cycle, data in
the master and the slave are interchanged.
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