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參數(shù)資料
| 型號(hào)： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁(yè)數(shù)： | 84/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
84 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 86. Fifth Interrupt Register
Name
Base
Default
IRQENRD_4
2-wire serial
00h
Offset: 27h
Fifth Interrupt Register
Please be aware that writing to this register will enable/disable the
corresponding interrupts, while reading gets the actual interrupt status and
will clear the register at the same time. It is not possible to read back the
interrupt enable/disable settings. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7:6
T_DEB<1:0>
00
R/W
Sets the USB and Charger connect de-bounce time:
00: 512ms
01: 256ms
10: 128ms
11: 0ms
5
AVDD27_IRQ
0
W
Enables interrupt for under-voltage supervision of AVDD27
0: disable
1: enable
AVDD27_under
x
R
This bit is set when a -5% under-voltage at AVDD27 occurs
4
DCDC15_IRQ
0
W
Enables interrupt for over-voltage supervision of SW15
0: disable
1: enable
DCDC15_over
x
R
This bit is set when SW15 exceeds 15V.
3
-
0
n/a
2
REM_DET
(edge)
0
W
Microphone remote key press detection interrupt setting
0: disable
1: enable
x
R
Microphone remote key press detection interrupt reading
0: no key press detected
1: Microphone supply current got increased, remote key press
detected -> measure MICS supply current
1
RTC_UPDATE
(edge)
W
RTC timer interrupt setting
0: disable
1: enable
x
R
RTC timer interrupt reading
0: no RTC interrupt occurred
1: RTC timer interrupt occurred. Selecting minute or second
interrupt can be done via RTCT register (29h)
0
ADC_EOC
(edge)
0
W
ADC end of conversion interrupt setting
0: disable
1: enable
x
R
ADC end of conversion interrupt reading
0: ADC conversion not finished
1: ADC conversion finished. Read out ADC_0 and ADC_1
register to get the result (2Eh & 2Fh)
ams
AG
Technical
content
still
valid
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