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| 型號： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數(shù)： | 29/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標準包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應商設(shè)備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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Revision 1.11
34 - 91
AS3543 3v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s
Low ripple, low noise operation:
In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the
PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil
current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low
input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip
mode.
Figure 22. DCDC buck with disabled current force / pulse skip mode
1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage
High efficiency operation:
In this mode there is a minimum coil current necessary before switching off the PMOS. As result, fewer pulses at low
output loads are necessary, and therefore the efficiency at low output load is increased. On the other hand the output
voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current.
Figure 23. DCDC buck with enabled current force / pulse skip mode
1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage
It’s also possible to switch between these two modes dynamically during operation:
100% PMOS ON mode for low dropout regulation:
For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which
is than in LDO mode. This feature is enabled if the output voltage drops by more than 4%.
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