參數(shù)資料
型號： AS3543-ECTP
廠商： ams
文件頁數(shù)： 47/92頁
文件大?。?/td> 0K
描述： IC CODEC AUDIO FRONT END 68CTBGA
標準包裝： 4,000
類型： 音頻編解碼器
應用： 便攜式音頻，電話
安裝類型： 表面貼裝
封裝/外殼： 68-TFBGA
供應商設備封裝： 68-CTBGA（6x6）
包裝： 帶卷 (TR)
www.austriamicrosystems.com
Revision 1.11
50 - 91
AS3543 3v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
10.6.4 Register Description
10.7
GPIO Pins
10.7.1 General
PWGD, XRES, Q24M, Q32K, SDO, XIRQ are so called GPIO (general purpose inputs/outputs) as they can feature
auxiliary functionality.
If the main pin function is not needed all pins can provide internal clocks or can drive a static HIGH or LOW. Four differ-
ent clock lines (CLKINT1, CLKINT2, CLK24M, CLK32K) can be selected. Each of these clock lines can drive different
frequencies which can be set by register options. In addition some pins can provide a PWM signal. The duty cycle of
the PWM output can also be set in the registers.
PWGD, XRES and XIRQ can be configured also as open drain outputs. For all pins the driver strength of the push/pull
output mode can be selected.
PWGD, Q24M, Q32K can also be used as inputs for a heartbeat signal or an external dimming signal for the DCDC15
booster.
10.7.2 Internal Source Signals
CLKINT1 Signal
This is an internal signal line which can drive pre defined frequencies of 125Hz, 1kHz, 667kHz or 2MHz. This signal
line can be selected as source for the XRES, Q24M, Q32K, XIRQ and SDO GPIO output pins.
CLKINT2 Signal
This is an internal signal line which can drive the PLL clock, the clock for the logarithmic dimming of DCDC15 or can
be set to static HIGH/LOW. This signal line can be selected as source for the PWGD, Q24M, Q32K and XIRQ output
pins.
CLK24M Signal
This is an internal signal line which is driving the 12-24MHz oscillator output clock per default, but can be set to drive
this clock divided by 2 or 4. The forth option is to deactivate the 12-24MHz oscillator.
CLK32K Signal
This is an internal signal line which is driving the 32kHz oscillator output clock per default, but can be set to drive also
a 1Hz signal as well as a a static HIGH/LOW.
PWM Signal
The duty cycle of the PWM signal can be set in 128 steps plus an option to invert the signal. It ca be used as source for
all GPIO outputs other than XIRQ.
10.7.3 Pin Functions
PWGD Pin
Can drive CLK24M, CLKINT2 or the PWM signal as auxiliary function. The output can be configured to operate in
push/pull (2 different driver strength) open-drain mode or to be trie-state. It can be used as an input for a heartbeat,
external dimming signal or as additional source for the 10-bit general purpose ADC.
Using a capacitor on this pin will delay the XRES signal. Please refer to chapter XRES delay with PWGD pin on page
44. When usig the pin as an ADC input the voltage to be measurted has to be higher than 1V, the XRES delay function-
ality is than no longer avilable.
Table 39. ADC10 Related Register
Name
Base
Offset
Description
2-wire serial
1Ch
Extended ADC source selection
2-wire serial
27h
Interrupt settings for end of conversion interrupt
2-wire serial
2Eh
ADC source selection, ADC result<9:8>
2 wire serial
2Fh
ADC result <7:0>
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