參數(shù)資料
型號(hào)： AM49LV128BML11NT
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： 128 Megabit (8 M x 16-Bit) MirrorBit⑩ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA64
封裝： 12 X 9 MM, FBGA-64
文件頁(yè)數(shù)： 61/98頁(yè)
文件大?。?/td> 1016K
代理商： AM49LV128BML11NT
June 17, 2004
Am49LV128BM
59
PSRAM AC CHARACTERISTICS
Read Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low
without change of address input of A3 to A20.
2. Address should not be changed within minimum t
RC.
3. The output load 50pF.
4. The output load 5pF.
5. Applicable to A3 to A20 when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 when CE1# is kept at Low
for the page address access.
7. In case Page Read Cycle is continued with keeping CE1#
stays Low, CE1# must be brought to High within 4
μ
s. In
other words, Page Read Cycle must be closed within 4
μ
s.
8. Applicable when at least two of address inputs among
applicable are switched from previous state.
9. t
RC
(min) and t
PRC
(min) must be satisfied.
Parameter
Symbol
t
RC
t
CE
t
OE
t
AA
t
BA
t
PAA
t
PRC
t
OH
t
CLZ
t
OLZ
t
BLZ
t
CHZ
t
OHZ
t
BHZ
t
ASC
t
ASO
t
AX
t
CHAH
t
OHAH
t
CP
Value
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
65
–
–
–
–
–
25
5
5
0
0
–
–
–
-5
10
–
-5
-5
12
Max.
1000
65
40
65
30
20
1000
–
–
–
–
20
20
20
–
–
Read Cycle Time (Notes 1, 2)
CE1# Access Time (Note 3)
OE# Access Time (Note 3)
Address Access Time (Notes 3,5)
LB#/UB# Access Time (Note 3)
Page Address Access Time (Notes 3,6)
Page Read Cycle Time (Notes 1,6,7)
Output Data Hold Time (Note 3)
CE1# Low to Output Low-Z (Note 4)
OE# Low to Output Low-Z (Note 4)
LB#/UB# Low to Output High-Z (Note 4)
CE1# High to Output High-Z (Note 3)
OE# High to Output High-Z (Note 3)
LB#/UB# High to Output High-Z (Note 3)
Address Setup Time to CE1# Low
Address Setup Time to OE# Low
Address Invalid Time (Notes 5,8)
Address Hold Time from CE1# High (Note 9)
Address Hold Time from OE# High
CE1# High Pulse Width
–
–
–
相關(guān)PDF資料
PDF描述
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