參數(shù)資料
型號(hào)： AFE7222IRGCR
廠商： Texas Instruments
文件頁數(shù)： 47/106頁
文件大小： 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
REG_PDNI_TX : Power downs TX Channel A (I Channel) alone.
REG_PDNQ_TX : Power downs TX Channel B (Q Channel) alone.
REG_PDNI_RX : Power downs RX Channel A (I Channel) alone.
REG_PDNQ_RX : Power downs RX Channel B (Q Channel) alone.
REG_PDN_FRM_REG has a similar role to play for the above modes (REG_PDNI_TX, REG_PDNQ_TX,
REG_PDNI_RX, REG_PDNQ_RX). When REG_PDN_FRM_REG is low, it configures the PDN pin to the
function of the bit that is set. When REG_PDN_FRM_REG is high, the set bit directly controls the
described powerdown mode.
MODE_LP_CMOS : Low power RX CMOS mode. When the RX interface is set to CMOS interface, the
device power can be lowered by about 20 mW by setting this bit. Use this mode only for Fs less than 40
MSPS. Refer to section Low power RX CMOS mode.
REG_SINGLE : Setting this bit power downs one ADC (Channel A) and One DAC (Channel A). The
output data format is SDR. In this mode DAC Channel B and ADC Channel B are active.
Register Name – CONFIG110 – Address 0x209, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
REG_OEZ_
LVDS_ CHB
LVDS_ CHA
LVDS_CLK
CMOS_ CLK
CMOS_DAT
REG_OEZ_CMOS_DAT: 3-state RX CMOS data buffers (use for Half Duplex TX mode when using
CMOS interface)
REG_OEZ_CMOS_CLK: 3-state RX CMOS clock buffer (use for Half Duplex TX mode when using CMOS
interface)
REG_OEZ_LVDS_CLK: 3-state RX LVDS clock buffer (use for Half Duplex TX mode when using LVDS
interface)
REG_OEZ_LVDS_CHA: 3-state RX LVDS data buffers for Channel A (use for Half Duplex TX mode when
using LVDS interface)
REG_OEZ_LVDS_CHB: 3-state RX LVDS data buffers for Channel B (use for Half Duplex TX mode when
using LVDS interface)
Register Name – CONFIG111 – Address 0x20A, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
REG_SE_CLK
REG_LVDS_TX
REG_LVDS_RX
WHAT_IS_SDOUT<1:0>
REG_SE_CLK: When set, the device is configured to expect two single ended clocks on CLKINP and
CLKINN. DAC_CLK gets derived from the clock on CLKINN and ADC_CLK from the clock on CLKINP.
The differential clock buffer is turned off, saving about 6mA of current on the 1.8 V supply.
REG_LVDS_TX: By default both RX and TX interfaces are in CMOS mode, this bit sets the TX input
interface in LVDS mode
REG_LVDS_RX: this bit sets the RX output interface in LVDS mode. In addition to setting this bit, also set
bit MASTER_OVERRIDE_RX (in CONFIG131) for proper LVDS settings.
WHAT_IS_SDOUT<1:0>: Configures the SDOUT pin.
WHAT_IS_SDOUT<1:0>
Mode
00
Floating
01
Analog test o/p (Do not use)
10
Digital o/p (Use for Aux ADC and register readout)
11
Digital i/p (Use for Aux DAC input mode)
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
45
Product Folder Link(s): AFE7222 AFE7225
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